Support

Support Options

Submit a Support Ticket

 

Reed-Muller Reversible Logic Synthesizer (RMRLS) 0.2

By James Donald1, Pallav Gupta2

1. NVIDIA 2. VIllanova University

See also

No results found.

Category

Downloads

Published on

Abstract

Reed-Muller Reversible Logic Synthesis tool (a.k.a. RELOS) is a tool for the synthesis of reversible functions based on positive-polarity Reed-Muller expressions. The second release of RMRLS features reversible logic synthesis with SWAP, Fredkin, and Peres gates.

Credits

This work was done under the supervision of Professor Niraj K. Jha. The student involved was James Donald.

Sponsored by

NSF

References

1. J. Donald and N. K. Jha. "Reversible Logic Synthesis with Fredkin and Peres Gates." ACM Journal Emerging Technologies Computing Systems, 2008 (accepted for publication).
2. P. Gupta, A. Agrawal, and N. K. Jha. "An Algorithm for Synthesis of Reversible Logic Circuits." IEEE Trans. Computer-Aided Design, vol. 24, no. 1, Nov. 2006.
3. A. Agrawal and N. K. Jha, "Synthesis of Reversible Logic." Design Automation and Test in Europe Conf., Feb. 2004.

Cite this work

Researchers should cite this work as follows:

  • James Donald; Pallav Gupta (2008), "Reed-Muller Reversible Logic Synthesizer (RMRLS) 0.2," https://nanohub.org/resources/3775.

    BibTex | EndNote

Tags

nanoHUB.org, a resource for nanoscience and nanotechnology, is supported by the National Science Foundation and other funding agencies. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.