Simulate the nanoscale multigate-FET structures (finFET and nanowire) using drift diffusion approaches

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Archive Version 1.0
Published on 01 May 2008, unpublished on 24 Nov 2008
Latest version: 1.1.5. All versions

doi:10.4231/D35Q4RK62 cite this

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MuGFET is the simulation tool for nano-scale multi-gate FET structure
MuGFET users can either use the PROPHET or the PADRE tools which provide self-consistent solutions to the Poisson and drift-diffusion equation.

The tool is supported by a First Time User Guide.

At the nanometer scale quantum transport approaches that are based on a full 3D Poisson-Schroedinger solution like the nanowire Lab or the atomistically resolved Bandstructure Lab are needed to provide insight into transport. However, for devices that are 10nm or larger semi-classical approaches can provide some significant insight. For device domains 30nm or larger, quantum approaches as implemented in today's simulators, may not contain enough physics of scattering and dephasing. Therefore there are some advantages in using classical simulation approaches over quantum simulation approaches for certain classes of device regimes. Drift and diffusion simulations are significantly faster than quantum ballistic simulations and also fairly well fitted the experimental results.

PROPHET is a PDE (partial differential equation) solver for 1, 2, or 3 dimension. In PROPHET, equations are extensible and flexible in geometry. So it is used in more general-purpose physics simulation.

PADRE is a device-oriented simulator for 2D/3D device with arbitrary geometry. It provides many useful plots for engineers and deep understanding of physics. Many options are provided with respect to the numerical methods and semiconductor device physics.

MuGFET is user-friendly graphical user interface and provides a lot of useful plots such as subthreshold, DIBL, on/off current ratio, etc. Users don't have to calculate these parameters by themselves.

The tool is supported by a First Time User Guide.

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X. Huang et al., "Sub 50-nm FinFET: PMOS" , IEDM ,1999
A. Breed and K. P. Roenker, "Device Simulation Study of Silicon P-Channel FinFETs", IEEE, 2005
Sung Dae Suk, et al.,"High Performance 5nm radius Twin Silicon Nanowire MOSFET(TSNWFET) : Fabrication on Bulk Si Wafer, Characteristics, and Reliability", IEDM 2005, pp 717-720, Dec 2005
Saumitra R. Mehrotra, “A simulation study on silicon nanowire field effect transistors(FETs)”, thesis, 2007

Cite this work

Researchers should cite this work as follows:

  • SungGeun Kim; Gerhard Klimeck; Sriraman Damodaran; Benjamin P Haley (2014), "MuGFET," (DOI: 10.4231/D35Q4RK62).

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