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Digital design flow is a lengthy process that involves many steps to take the design from RTL to the system testing phase. The objective of this webinar is to demystify this field and provide in-depth understanding of the different transformations that occur in each design step, and how these transformations can affect the final performance metrics. The webinar will focus on FPGAs as the target technology. FPGA is a very powerful technology to implement complex System on Chip (SoCs) in an efficient way and in extremely fast time to market. With the recent advancements in their architecture, speed, power efficiency, and peripherals, FPGAs breached almost every field from IoT to space and military applications.

Specifically, this webinar will focus on fundamental elements in the design process, including HDL modeling, event‑driven simulation, synthesis, timing analysis, and FPGA architecture.

To see the schedule for upcoming live webinars please visit the MEST Webinar Calendar.

Srini Devadas is the Webster Professor of Electrical Engineering and Computer Science and has has been on the MIT EECS faculty since 1988. He served as Associate Head of the Department of Electrical Engineering and Computer Science, with responsibility for Computer Science, from 2005 to 2011.

Devadas’s research interests span Computer-Aided Design (CAD), computer security and computer architecture and he has received significant awards from each discipline. In 2015, he received the ACM/IEEE A. Richard Newton Technical Impact award in Electronic Design Automation. He received the IEEE Computer Society Technical Achievement Award in 2014 for inventing Physical Unclonable Functions and single-chip secure processor architectures. Devadas’s work on hardware information flow tracking published in the 2004 ASPLOS received the ASPLOS Most Influential Paper Award in 2014. His papers on analytical cache modeling and the Aegis single-chip secure processor were included as influential papers in “25 Years of the International Conference on Supercomputing.” In 2017 he received the IEEE W. Wallace McDowell Award for contributions to secure hardware. He is an IEEE and ACM Fellow.

Devadas has taught widely in EECS, lecturing classes in VLSI, discrete mathematics, computer architecture, algorithms and software engineering. He is a MacVicar Faculty Fellow and an Everett Moore Baker teaching award recipient, considered MIT’s two highest undergraduate teaching honors.

National Microelectronics Security Training Center (MEST).

Researchers should cite this work as follows:

• Srini Devadas (2024), "W24 - Towards Secure High-Performance Computer Architectures," https://nanohub.org/resources/39029.

  BibTex | EndNote

1. chip design
2. FPGAs
3. Hardware Security
4. MEST
5. security
6. System-on-Chip (SoC)