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Various low-dimensional materials are currently explored for future electronics applications. The common ground for all these structures is that the surface related impact can no longer be ignored – the common approach applied to predict properties of bulk-type three-dimensional (3D) materials. Relevant surface related effects could be e.g. surface roughness scattering or it could mean that the broken symmetry at the interface causes quantization effects that alter the entire band structure and result in a completely new type of material class. Examples of nano- materials under current extensive study include: nanotubes, nanowires and graphene. While understanding the novel properties of these materials is relevant in itself and does not need any further justification, the stakes are different when nano-materials are discussed for electronics applications.

Here we discuss some recent experimental results on carbon nanotube field-effect transistors as well as a contact study on a novel type of silicon nanowire device. The aim is to close the gap between the current state-of-the art understanding of pure materials properties and actual applications. It will be discussed in how far carbon nanotubes are useful for low-power applications [1,2] and how ultimate scaling can be achieved. In the case of silicon nanowires it will be highlighted why extraction of intrinsic properties is still a challenge and how process modules need to be carefully adjusted to the particular challenges posed by this new material class [3].

Dr. J. Appenzeller received the M.S. and Ph.D. degrees in physics from the Technical University of Aachen, Germany in 1991 and 1995. His Ph.D. dissertation investigated quantum transport phenomena in low dimensional systems based on III/V heterostructures. He worked for one year as a Research Scientist in the Research Center in Juelich, Germany before he became an Assistant Professor with the Technical University of Aachen in 1996. During his professorship he explored mesoscopic electron transport in different materials including carbon nanotubes and superconductor-semiconductor-hybride devices. From 1998 to 1999, he was with the Massachusetts Institute of Technology, Cambridge, as a Visiting Scientist, exploring the ultimate scaling limits of silicon MOSFET devices. From 2001 until 2007, he had been with the IBM T.J. Watson Research Center, Yorktown, NY, as a Research Staff Member mainly involved in the investigation of the potential of carbon nanotubes and silicon nanowires for a future nanoelectronics. Since 2007 he is Professor of Electrical and Computer Engineering at Purdue University and Scientific Director of Nanoelectronics in the Birck Nanotechnology Center. His current interests include novel devices based on low-dimensional nano-materials as nanowires, nanotubes and graphene.

ECE Graduate Seminar Series

1. Appenzeller, Y.-M. Lin, J. Knoch, and Ph. Avouris, Phys. Rev. Lett. 93, 196805 (2004).
2. J. Appenzeller, Y.-M. Lin, J. Knoch, and Ph. Avouris, IEEE Transactions on Electron Devices 52, 2568 (2005).
3. J. Appenzeller, J. Knoch, E. Tutuc, M. Reuter, and S. Guha, IEDM Technical Digest, 555 (2006).

Researchers should cite this work as follows:

• Joerg Appenzeller (2008), "What Promises do Nanotubes and Nanowires Hold for Future Nanoelectronics Applications?," https://nanohub.org/resources/4059.

  BibTex | EndNote

1. carbon nanotubes
2. CNTFET
3. devices
4. graphene
5. nanoelectronics
6. nanotransistors
7. nanotubes
8. nanowires
9. research seminar
10. tunneling