Support

Support Options

Submit a Support Ticket

 

Universality of NBTI-Induced Interface Trap Generation and Its Impact on ID Degradation in Strained/ Unstrained PMOS Transistors

By Ahmad Ehteshamul Islam1, Muhammad A. Alam2

1. Air Force Research Laboratory 2. Purdue University

M. Ashraful Alam Research Group

This resource belongs to the M. Ashraful Alam Research Group group.

See also

No results found.

Published on

Abstract

Despite extensive use of strained technology, it is still unclear whether NBTI-induced NIT generation in strained transistors is substantially different from that of unstrained ones. Here, we present a comprehensive theory for NIT generation in strained/unstrained transistors and show its universality over a wide range of strain. We further propose that an appropriately designed/optimized transistor might reduce/eliminate NBTI being a concern for CMOS scaling.

Credits

Brick Nanotechnology Center for Experiment
Khaled Ahmed (Applied Materials) for Devices
Souvik Mahapatra (IIT-Bombay) and Abu Naser Zainuddin (Purdue) for Discussions

Publications

A. E. Islam, J. H. Lee, W. H. Wu, A. Oates and M. A. Alam, "Universality of Interface Trap Generation and Its Impact on ID Degradation in Strained/Unstrained PMOS Devices During NBTI Stress," International Electron Devices Meeting (IEDM) 2008, pp. 107-110

Cite this work

Researchers should cite this work as follows:

  • Ahmad Ehteshamul Islam; Muhammad A. Alam (2008), "Universality of NBTI-Induced Interface Trap Generation and Its Impact on ID Degradation in Strained/ Unstrained PMOS Transistors," https://nanohub.org/resources/6067.

    BibTex | EndNote

Tags

nanoHUB.org, a resource for nanoscience and nanotechnology, is supported by the National Science Foundation and other funding agencies. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.