Despite extensive use of strained technology, it is still unclear whether NBTI-induced NIT generation in strained transistors is substantially different from that of unstrained ones. Here, we present a comprehensive theory for NIT generation in strained/unstrained transistors and show its universality over a wide range of strain. We further propose that an appropriately designed/optimized transistor might reduce/eliminate NBTI being a concern for CMOS scaling.

Brick Nanotechnology Center for Experiment
Khaled Ahmed (Applied Materials) for Devices
Souvik Mahapatra (IIT-Bombay) and Abu Naser Zainuddin (Purdue) for Discussions

A. E. Islam, J. H. Lee, W. H. Wu, A. Oates and M. A. Alam, "Universality of Interface Trap Generation and Its Impact on ID Degradation in Strained/Unstrained PMOS Devices During NBTI Stress," International Electron Devices Meeting (IEDM) 2008, pp. 107-110

Researchers should cite this work as follows:

• Ahmad Ehteshamul Islam, Muhammad A. Alam (2008), "Universality of NBTI-Induced Interface Trap Generation and Its Impact on ID Degradation in Strained/ Unstrained PMOS Transistors," https://nanohub.org/resources/6067.

  BibTex | EndNote

1. Degradation-free transistor
2. Drain Current Degradation
3. Effective Mobility
4. Interface Traps
5. nanoelectronics
6. Reaction-Diffusion Model
7. strain