In the coming decade, CMOS technology is expected to approach its scaling limitations. Among the proposed nanotechnologies, nanowires have the edge in the size of circuits and logic arrays that have already been fabricated and experimentally evaluated. For this technology, logic-level design methodologies are being developed. The time has now come to develop automated tools for implementing VLSI designs using nanowires. In this project, we present a design automation tool, called NanoV, to fulfill this need for nanowires. It is a complete logic-to-layout tool with built-in defect-aware steps since the defect levels in nanotechnologies are expected to be relatively high (between 1 to 10%). We calculate area/delay/power results for given circuit definitions implemented using our tool.
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