VALint: the NEEDS Verilog-A Checker (BETA)

By Xufeng Wang1, Geoffrey Coram2, Colin McAndrew3

1. Purdue University 2. Analog Devices, Inc. 3. Freescale Semiconductor

Verilog-A lint and pretty printer created by NEEDS

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Version 1.0.0 - published on 31 Mar 2017

doi:10.4231/D3HX15S0V cite this

Open source: license | download

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Recent Questions (1-3 of 3)
1691 Difference between “parameter real” and “real”
Asked by Saurabh Vinayak Suryavanshi Open 0
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1654 segmentation fault?
Asked by Geoffrey Coram Open 1
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1653 issue with Makefile
Asked by Geoffrey Coram Open 0
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