VALint: the NEEDS Verilog-A Checker (BETA)

By Xufeng Wang1, Geoffrey Coram2, Colin McAndrew3

1. Purdue University 2. Analog Devices, Inc. 3. Freescale Semiconductor

Verilog-A lint and pretty printer created by NEEDS

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Version 1.0.0 - published on 31 Mar 2017

doi:10.4231/D3HX15S0V cite this

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Recent Wishes (14)
796 add warning for unused parameters
Proposed by Geoffrey Coram @
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778 clean up Makefile -- don't configure every time
Proposed by Geoffrey Coram @
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775 Flag (mis)use of bit-wise operators
Proposed by Geoffrey Coram @
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764 Scroll bar in output window
Proposed by Geoffrey Coram @
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763 Not an error to use ddx() in noise calculations
Proposed by Geoffrey Coram @
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762 Not an error to reference global ground in ddx() call
Proposed by Geoffrey Coram @
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758 Installation and usage document
Proposed by Anonymous @
points 0 Like 0 Dislike Accepted
752 way to ignore particular warnings
Proposed by Geoffrey Coram @
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751 improve handling of macros
Proposed by Geoffrey Coram @
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782 upload window does not close automatically
Proposed by Geoffrey Coram @
  0 Like 0 Dislike Granted
777 change name of binary
Proposed by Geoffrey Coram @
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750 click warning/line number in log file and jump to corresponding line in source code window
Proposed by Geoffrey Coram @
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749 line numbers in source code window
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748 resizable log window
Proposed by Geoffrey Coram @
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