2011 NCN@Purdue Summer School: Electronics from the Bottom Up
20 Jul 2011 |
click on image for larger versionAlumni Discussion Group: LinkedIn
How to simulate the GaN Power Device model
Closed | Responses: 0
I’m new to device modeling and I want to numerically simulate GaN device equations using...
a TCAD Lab
Introduction to TCAD Simulation
The existing semiconductor industry is now fundamentally built on the assumption that almost every aspect of a chip is first designed in software.
A UCSD analytic TFET model
18 Dec 2015 | | Contributor(s):: Jianzhi Wu, Yuan Taur
A continuous, analytic I-V model is developed for double-gate and nanowire tunnel FETs with 3D density of states, including depletion in the source. At the core of the model is a gate-controlled channel potential that satisfies the source and drain boundary conditions. Verified by...
A Verilog-A Compact Model for Negative Capacitance FET
28 Nov 2015 | Compact Models | Contributor(s):
By Muhammad Abdul Wahab1, Muhammad A. Alam1
The NC-FET compact model is a semi-physical verilog-A model of the negative capacitance transistor. We developed this self-consistent model with BSIM4/MVS and Landau theory. This model is useful to...
ABACUS - Assembly of Basic Applications for Coordinated Understanding of Semiconductors
16 Jul 2008 | | Contributor(s):: Xufeng Wang, Daniel Mejia, Dragica Vasileska, Gerhard Klimeck
One-stop-shop for teaching semiconductor devices
Ahmad Ehteshamul Islam
Atomistic Modeling of Nano Devices: From Qubits to Transistors
12 Apr 2016 | | Contributor(s):: Rajib Rahman
In this talk, I will describe such a framework that can capture complex interactions ranging from exchange and spin-orbit-valley coupling in spin qubits to non-equilibrium charge transport in tunneling transistors. I will show how atomistic full configuration interaction calculations of exchange...
Atomistic Simulations of Reliability
01 Jul 2010 | | Contributor(s):: Dragica Vasileska
Discrete impurity effects in terms of their statistical variations in number and position in the inversion and depletion region of a MOSFET, as the gate length is aggressively scaled, have recently been researched as a major cause of reliability degradation observed in intra-die and die-to-die...