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Effect of the High-k Dielectric/Semiconductor Interface on Electronic Properties in Ultra-thin Channels
15 Oct 2015 | Online Presentations | Contributor(s): Daniel A. Valencia-Hoyos, Evan Michael Wilson, mark rodwell, Gerhard Klimeck, Michael Povolotskyi
IWCE 2015 presentation. Abstract and more information to be added at a later date. As logic devices continue to downscale, an increasing fraction of the channel atoms are in close contact...
Theory and characterization of random defect formation and its implication in variability of nanoscale transistors
30 Sep 2011 | Papers | Contributor(s): Ahmad Ehteshamul Islam
Over the last 50 years, carrier transport has been the central research topic in the semiconductor area. The outcome was a dramatic improvement in the performance of a transistor, which is one of...
A methodology for SPICE-compatible modeling of nanoMOSFETs
17 Nov 2010 | Teaching Materials | Contributor(s): Alba Graciela Avila, David Espejo
An original SPICE-compatible model for Intel's 45nm High-K MOSFET is presented. It takes into account some Quantum-Mechanical Effects that occur at small scale like Channel Length Modulation...