Tags: Memory

All Categories (1-13 of 13)

  1. Unimore Resistive Random Access Memory (RRAM) Verilog-A Model

    22 May 2019 | Compact Models | Contributor(s):

    By Francesco Maria Puglisi1, Tommaso Zanotti1, Paolo Pavan1

    Università di Modena e Reggio Emilia

    The Unimore RRAM Verilog-A model is a physics-based compact model of bipolar RRAM which includes cycle-to-cycle variability, thermal effects, self-heating, and multilevel Random Telegraph Noise (RTN).

    https://nanohub.org/publications/289/?v=1

  2. Sebastian Jan Juchnowski

    https://nanohub.org/members/197883

  3. Sun

    https://nanohub.org/members/127172

  4. san k p

    https://nanohub.org/members/125452

  5. Abdelmalek Benkouider

    Over five years of experience in scientific research within academic institutes and industrial R&D departments, with strong theoretical and experimental skills in nanotechnology. Demonstrated...

    https://nanohub.org/members/83692

  6. Illinois 2012: Aravind Alwan: Industry/Advisor

    02 May 2012 | | Contributor(s):: Aravind Alwan, Nadia Jassim

  7. Illinois 2012: Aravind Alwan: Design and simulation of Microsystems

    02 May 2012 | | Contributor(s):: Aravind Alwan, Nadia Jassim

  8. Illinois 2012: Feng Xiong: Industry/Advisor

    02 May 2012 | | Contributor(s):: Feng Xiong, Nadia Jassim

  9. Illinois 2012: Feng Xiong: Phase Change Memory

    02 May 2012 | | Contributor(s):: Feng Xiong, Nadia Jassim

  10. Esteve Amat

    https://nanohub.org/members/52897

  11. Comparisons of macrospin and OOMMF simulations

    26 Jan 2010 | | Contributor(s):: Dmitri Nikonov, George Bourianoff

    Plots of switchign time of nanomagnets by spin torque calculated by macrospin model and micromagnetic tool OOMMF, compared side-by-side. D. E. Nikonov, G. I. Bourianoff, G. Rowlands, I. N. Krivorotov Should be read and cited in conjunction with http://arxiv.org/abs/1001.4578

  12. Memristor Simulation Tool

    05 Oct 2009 | | Contributor(s):: Yuan Shen, Sansiri Tanachutiwat, Wei Wang

    Simulate resistance change of a Voltage-controlled Memristor

  13. Illinois ECE 498AL: Programming Massively Parallel Processors, Lecture 9: Memory Hardware in G80

    26 Aug 2009 | | Contributor(s):: Wen-Mei W Hwu

    Memory Hardware in G80Topics: CUDA Device Memory Space Parallel Memory Sharing SM Memory Architecture SM Register File Programmer view of Register File Matrix Multiplication Example More on Dynamic Partitioning ILP vs. TLP Memory Layout of a Matrix in C Constants Shared Memory Parallel Memory...