Tags: MOSFET

Description

The metal–oxide–semiconductor field-effect transistor is a device used for amplifying or switching electronic signals. In MOSFETs, a voltage on the oxide-insulated gate electrode can induce a conducting channel between the two other contacts called source and drain. The channel can be of n-typeor p-type, and is accordingly called an nMOSFET or a pMOSFET (also commonly nMOS, pMOS). It is by far the most common transistor in both digital and analog circuits, though the bipolar junction transistor was at one time much more common. More information on MOSFET can be found here.

All Categories (101-120 of 143)

  1. MOSfet Homework Assignment - Role of Dielectric Constant and Thickness

    31 Jan 2008 | | Contributor(s):: David K. Ferry

    Use the MOSfet tool on nanoHUB to simulate a n-channel MOSFET with the following parameters:Lsd=LG=45nm (each 15 nodes), oxide thickness of 1.2 nm (K=3.9, 5 nodes),poly-Si gate, junction depth of 10 nm (20 nodes), and all other parametersat their nominal preset values.Now, change K to 20, and the...

  2. MOSFET Lab - Scaling

    02 Jan 2011 | | Contributor(s):: Saumitra Raj Mehrotra, Gerhard Klimeck, Dragica Vasileska

    The concept of device scaling and the need to control short channel effects is used in this real life problem

  3. MOSFET Lab Exercise: Series Resistance and Transistor Breakdown

    12 Jul 2011 | | Contributor(s):: Dragica Vasileska, Gerhard Klimeck

    This exercise is supposed to teach the students the role of the source and drain resistance on device output characteristics. The second portion of the assignment is supposed to train students how to simulate MOSFET operation near transistor breakdown.

  4. MOSFet Learning Materials

    By completing the MOSFET Lab in ABACUS - Assembly of Basic Applications for Coordinated Understanding of Semiconductors, users will be able to understand a) the operation of MOSFET devices, b) the...

    https://nanohub.org/wiki/MOSFETLabPage

  5. MOSFET Simulation

    04 Oct 2013 | | Contributor(s):: Chen Shang, Sankarsh Ramadas, Tanya Faltens, derrick kearney, Krishna Madhavan

    Displays drain current as a function of source-drain voltage for different values of gate voltage, gate dimensions, substrate material, and oxide material in an n-type MOSFET.

  6. MOSFET Worked out problems 1

    06 Dec 2010 | | Contributor(s):: Saumitra Raj Mehrotra, Gerhard Klimeck

    Short channel effects in a MOSFET due to channel length scaling are highlighted in this worked out problem.

  7. MOSFet: First-Time User Guide

    13 Jun 2009 | | Contributor(s):: Saumitra Raj Mehrotra, Benjamin P Haley

    This first-time user guide provides introductory material to MOSFet on nanoHUB. The introduction to MOSFETs and SOI-MOSFETs is followed by a tour of the Rappture interface, which notes key inputs and typical outputs. We discuss the default simulation (what happens if you don't change any inputs,...

  8. MSE 376 Lecture 12: Nanoscale CMOS, part 1

    31 Mar 2007 |

  9. MSE 376 Lecture 13: Nanoscale CMOS, part 2

    31 Mar 2007 |

  10. Nanoelectronic Modeling Lecture 40: Performance Limitations of Graphene Nanoribbon Tunneling FETS due to Line Edge Roughness

    05 Aug 2010 | | Contributor(s):: Gerhard Klimeck, Mathieu Luisier

    This presentation the effects of line edge roughness on graphene nano ribbon (GNR) transitors..Learning Objectives:GNR TFET Simulation pz Tight-Binding Orbital Model 3D Schrödinger-Poisson Solver Device Simulation Structure Optimization (Doping, Lg, VDD) LER => Localized Band Gap States LER =>...

  11. Nanoelectronics and the Future of Microelectronics

    22 Aug 2002 | | Contributor(s):: Mark Lundstrom

    Progress in silicon technology continues to outpace the historic pace of Moore's Law, but the end of device scaling now seems to be only 10-15 years away. As a result, there is intense interest in new, molecular-scale devices that might complement a basic silicon platform by providing it...

  12. nanoMOS 2.0: A Two -Dimensional Simulator for Quantum Transport in Double-Gate MOSFETs

    06 Oct 2006 | | Contributor(s):: Zhibin Ren, Ramesh Venugopal, Sebastien Goasguen, Supriyo Datta, Mark Lundstrom

    A program to numerically simulate quantum transport in double gate MOSFETs is described. The program uses a Green’s function approach and a simple treatment of scattering based on the idea of so-called Büttiker probes. The double gate device geometry permits an efficient mode space approach that...

  13. Nanoscale MOSFETs: Physics, Simulation and Design

    26 Oct 2006 |

    This thesis discusses device physics, modeling and design issues of nanoscale transistors at the quantum level. The principle topics addressed in this report are 1) an implementation of appropriate physics and methodology in device modeling, 2) development of a new TCAD (technology computer aided...

  14. Nanoscale MOSFETS: Physics, Simulation and Design

    27 Jun 2013 | | Contributor(s):: Zhibin Ren

    This thesis discusses device physics, modeling and design issues of nanoscale transistors at the quantum level. The principle topics addressed in this report are 1) an implementation of appropriate physics and methodology in device modeling, 2)development of a new TCAD (technology computer aided...

  15. Nanoscale Transistors Lecture 11: MOSFET Limits and Possibilities

    19 Jul 2012 | | Contributor(s):: Mark Lundstrom

  16. Negative Bias Temperature Instability (NBTI) in p-MOSFETs: Characterization, Material/Process Dependence and Predictive Modeling

    25 Mar 2012 | | Contributor(s):: Souvik Mahapatra

    This is a presentation on Negative Bias Temperature Instability (NBTI), observed in p channel MOSFET devices. Though NBTI has been discovered more than 40 years ago, in the last 10 years it has become a very important reliability concern as the industry moved from thicker SiO2 to thinner SiON...

  17. Negative Bias Temperature Instability (NBTI) in p-MOSFETs: Characterization, Material/Process Dependence and Predictive Modeling (2011)

    06 May 2011 | | Contributor(s):: Souvik Mahapatra

    This is a presentation on Negative Bias Temperature Instability, or in short NBTI, observed in p channel MOSFET devices. Though NBTI has been discovered more than 40 years ago, in the last 10 years it has become a very important reliability concern as the industry moved from thicker SiO2 to...

  18. Negative Bias Temperature Instability (NBTI) in p-MOSFETs: Fast and Ultra-fast Characterization Methods (Part 1 of 3)

    26 Mar 2012 | | Contributor(s):: Souvik Mahapatra

  19. Negative Bias Temperature Instability (NBTI) in p-MOSFETs: Predictive Modeling (Part 3 of 3)

    25 Mar 2012 | | Contributor(s):: Souvik Mahapatra

    This is a presentation on Negative Bias Temperature Instability (NBTI), observed in p channel MOSFET devices. Though NBTI has been discovered more than 40 years ago, in the last 10 years it has become a very important reliability concern as the industry moved from thicker SiO2 to thinner SiON...

  20. Negative Bias Temperature Instability (NBTI) in p-MOSFETs: The Impact of Gate Insulator Processes (Part 2 of 3)

    25 Mar 2012 | | Contributor(s):: Souvik Mahapatra

    This presentation is part 2 on Negative Bias Temperature Instability (NBTI), observed in p channel MOSFET devices. Though NBTI has been discovered more than 40 years ago, in the last 10 years it has become a very important reliability concern as the industry moved from thicker SiO2 to thinner...