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Thermoelectric Device Compact Model
01 Sep 2015 | Compact Models | Contributor(s):
By Xufeng Wang1, Kyle Conrad1, Jesse Maassen1, Mark Lundstrom1
The NEEDS thermoelectric compact model describes a homogeneous segment of thermoelectric material and serves as a basic building block for complex electrothermal system.
Released Resonant Body Transistor with MIT Virtual Source (RBT-MVS) Model
30 Aug 2015 | Compact Models | Contributor(s):
By Bichoy W. Bahr1, Dana Weinstein1, Luca Daniel1
Massachusetts Institute of Technology (MIT)
An RBT is a micro-electromechanical (MEM) resonator with a transistor (FET) incorporated into the resonator structure to sense the mechanical vibrations. This is a fully-featured spice-compatible...
III-V Tunnel FET Model
20 Apr 2015 | Compact Models | Contributor(s):
By Huichu Liu1, Vinay Saripalli1, Vijaykrishnan Narayanan1, Suman Datta1
Penn State University
The III-V Tunnel FET Model is a look-up table based model, where the device current and capacitance characteristics are obtained from calibrated TCAD Sentaurus simulation.
19 Jan 2015 | Compact Models | Contributor(s):
By David M. Bromberg1, Daniel H. Morris1
Carnegie Mellon University
This model is a hybrid physics/empirical compact model that describes digital switching behavior of an mCell logic devices, where a write current moves a domain wall to switch the resistance of a...
21 Nov 2014 | Compact Models | Contributor(s):
By Colin McAndrew
Freescale Semiconductor, Inc.
Compact model for polysilicon (poly) resistors, 3-terminal JFETs, and diffused resistors.
FET pH Sensor Model
03 Nov 2014 | Compact Models | Contributor(s):
By Piyush Dak1, Muhammad A. Alam1
The FET pH sensor model is a surface potential compact model for FET based pH sensors that accurately describes the physics of electrolyte and surface charges that respond to pH.
Spin Switch Model
23 Oct 2014 | Compact Models | Contributor(s):
By Samiran Ganguly1, Kerem Yunus Camsari1, Supriyo Datta1
We present a circuit/compact model for the Spin Switch created using a Verilog-A based library of "spintronic lego blocks" building upon previous works on spin transport.
Stanford University Resistive-Switching Random Access Memory (RRAM) Verilog-A Model
By Zizhen Jiang1, H.-S. Philip Wong1
The Stanford University RRAM Model is a SPICE-compatible compact model which describes switching performance for bipolar metal oxide RRAM.
Purdue Nanoelectronics Research Laboratory Magnetic Tunnel Junction Model
By Xuanyao Fong1, Sri Harsha Choday1, Panagopoulos Georgios1, Charles Augustine1, Kaushik Roy1
This is the Verilog-A model of the magnetic tunnel junction developed by the Nanoelectronics Research Laboratory at Purdue University.
TAG Solar Cell Model (p-i-n thin film)
By Sourabh Dongaonkar1, Xingshu Sun1, Mark Lundstrom1, Muhammad A. Alam1
The TAG solar cell model is a physics-based compact model for p-i-n thin film solar cells that can be used for panel level simulations.
Released Resonant Body Transistor (RBT) Model
22 Oct 2014 | Compact Models | Contributor(s):
An RBT is a micro-electromechanical (MEM) resonator with a transistor (FET) incorporated into the resonator structure to sense the mechanical vibrations. The model is aimed to present a deep...
MIT Virtual Source GaNFET-RF ( MVSG-RF) Model
By Ujwal Radhakrishna1, Dimitri Antoniadis1
The MVS-G-RF GaN HEMT model is a self-consistent transport/capacitance model for scaled GaN HEMT devices used in RF applications.
Ambipolar Virtual Source Compact Model for Graphene FETs
By Shaloo Rakheja1, Dimitri Antoniadis1
This is a compact physics-based ambipolar-virtual-source (AVS) model that describes carrier transport in both unipolar and ambipolar regimes in quasi-ballistic graphene field-effect transistors...
TAG Solar Cell Model (p-i-n thin film) 1.0.0
02 Apr 2014 | | Contributor(s):: Sourabh Dongaonkar, Xingshu Sun, Mark Lundstrom, Muhammad A. Alam
A new Version of this resource has been released. Please see TAG Solar Cell Model (p-i-n thin film) 1.0.1. The TAG solar cell model is a physics-based compact model for p-i-n thin film solar cells that can be used for panel level simulations.
NEEDS Compact Model Development Process - v0.1
17 Feb 2014 | | Contributor(s):: Michael McLennan
The Nano-Engineered Electronic Device Simulation (NEEDS) effort is focused on creating compact models for nanoelectronics. The process involves a new Berkeley Model Development Environment (MDE) tool (https://nanohub.org/tools/mde) and other infrastructure on nanoHUB.org. This seminar describes...
RF Solid-State Vibrating Transistors
15 Feb 2014 | | Contributor(s):: Dana Weinstein
In this talk, I will discuss the Resonant Body Transistor (RBT), which can be integrated into a standard CMOS process. The first hybrid RF MEMS-CMOS resonators in Si at the transistor level of IBM’s SOI CMOS process, without any post-processing or packaging will be described. ...
Tunnel FETs - Device Physics and Realizations
10 Jul 2013 | | Contributor(s):: Joachim Knoch
Here, the operating principles of TFETs will be discussed in detail and experimental realizations as well as simulation results will be presented. In particular, the role of the injecting source contact will be elaborated on.
The Road Ahead for Carbon Nanotube Transistors
09 Jul 2013 | | Contributor(s):: Aaron Franklin
In this talk, recent advancements in the nanotube transistor field will be reviewed, showing why CNTFETs are worth considering now more than ever. Then, the material- and device-related challenges to realizing a nanotube-driven digital technology will be covered.
Device Physics Studies of III-V and Silicon MOSFETS for Digital Logic
28 Jun 2013 | | Contributor(s):: Himadri Pal
III-V's are currently gaining a lot of attraction as possible MOSFET channel materials due to their high intrinsic mobility. Several challenges, however, need to be overcome before III-V's can replace silicon (Si) in extremely scaled devices. The effect of low density-of-states of III-V materials...
III-V Nanoscale MOSFETS: Physics, Modeling, and Design
28 Jun 2013 | | Contributor(s):: Yang Liu
As predicted by the International Roadmap for Semiconductors (ITRS), power consumption has been the bottleneck for future silicon CMOS technology scaling. To circumvent this limit, researchers are investigating alternative structures and materials, among which III-V compound semiconductor-based...