Tags: tunnel FETs (TFET)

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Description

energy band diagram

The tunnel field-effect transistor (tunnel FET or TFET) is a transistor that operate by tunneling through the source/drain barrier rather than diffusion over the barrier. Tunnel FETs belongs to the family of so-called steep-slope devices which can switch on/off at lower voltages than metal oxide semiconductor FETs (MOSFETs) and are being investigated for ultra-low-power electronic applications.

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  1. THM-TFET Compact Model

    30 Apr 2022 | Compact Models | Contributor(s):

    By Alexander Kloes1, Fabian Horst2, Anita Farokhnejad3, Michael Graef4

    1. Technische Hochschule Mittelhessen 2. Bender GmbH & Co. KG 3. IMEC 4. Infineon Technologies

    THM-TFET is a compact model for a double-gate Tunnel-FET, is provided in Verilog-A code and allows for DC, AC and transient circuit simulation.

    https://nanohub.org/publications/427/?v=1

  2. IWCN 2021: Interfacial Trap Effects in InAs Gate-all-around Nanowire Tunnel Field- Effect Transistors: First-Principles-Based Approach

    15 Jul 2021 | | Contributor(s):: Hyeongu Lee, SeongHyeok Jeon, Cho Yucheol, Mincheol Shin

    In this work, we investigated the effects of the traps, Arsenic dangling bond (AsDB) and Arsenic anti-site (AsIn) traps, in InAs gate-all-around nanowire TFETs, using the trap Hamiltonian obtained from the first-principles calculations. The transport properties were treated by nonequilibrium...

  3. IWCN 2021: Ab initio Quantum Transport Simulation of Lateral Heterostructures Based on 2D Materials: Assessment of the Coupling Hamiltonians

    14 Jul 2021 | | Contributor(s):: Adel Mfoukh, Marco Pala

    Lateral heterostructures based on lattice-matched 2D materials are a promising option to design efficient electron devices such as MOSFETs [1], tunnel-FETs [2] and energy-filtering FETs [3]. In order to rigorously describe the transport through such heterostructures, an ab-initio approach based...

  4. Amir Sharfuddin

    https://nanohub.org/members/331936

  5. Compact Solver for Double-Gate Tunnel-FETs

    29 Mar 2021 | | Contributor(s):: Alexander Kloes, Fabian Horst, Anita Farokhnejad

    Plotting of DC and AC characteristics of DG-Tunnel-FETs using equations of the corresponding Verilog-A compact model THM-TFET.

  6. Siratun Nabi Sirat

    https://nanohub.org/members/186995

  7. Notre Dame TFET Model

    25 Aug 2017 | Compact Models | Contributor(s):

    By Hao Lu1, Trond Ytterdal2, Alan Seabaugh1

    1. University of Notre Dame 2. Norwegian University of Science and Technology

    Notre Dame TFET compact model version 2.1.0.

    https://nanohub.org/publications/195/?v=1

  8. MIT TFET compact model including the impacts of non-idealities

    03 May 2017 | Compact Models | Contributor(s):

    By Redwan Noor Sajjad1, Ujwal Radhakrishna2, Dimitri Antoniadis1

    1. Massachusetts Institute of Technology 2. Massachusetts Institute of Technology (MIT)

    We present a compact model for tunnel FET that for the first time fits experimental transfer and output characteristics including the impact of non-idealities such as trap assisted tunneling and...

    https://nanohub.org/publications/181/?v=1

  9. Is screening length in tunneling probability equation actually the tunneling barrier length?

    Q&A|Closed | Responses: 1

    Drain current of a TFET is proportioned to tunneling probability Tt. As it can be seen from the picture, Λ is screening length. my question is that can we call Λ, "tunneling...

    https://nanohub.org/answers/question/1858

  10. 15-Band Spectral Envelope Function Formalism Applied to Broken Gap Tunnel Field-Effect Transistors

    01 Nov 2016 | | Contributor(s):: Devin Verreck, Maarten Van de Put, Anne Verhulst, Bart Soree, G. Groeseneken, Ashish Dabral

    IWCE 2015 presentation.

  11. Auger Generation as an Intrinsic Limit to Tunneling Field-Effect Transistor Performance

    22 Sep 2016 | | Contributor(s):: Jamie Teherani

    Many in the microelectronics field view tunneling field-effect transistors (TFETs) as society’s best hope for achieving a > 10× power reduction for electronic devices; however, despite a decade of considerable worldwide research, experimental TFET results have significantly...

  12. Bhagwan Ram Raad

    https://nanohub.org/members/147680

  13. Achintya Priydarshi

    https://nanohub.org/members/145038

  14. A UCSD analytic TFET model

    18 Dec 2015 | | Contributor(s):: Jianzhi Wu, Yuan Taur

    A continuous, analytic I-V model is developed for double-gate and nanowire tunnel FETs with 3D density of states, including depletion in the source. At the core of the model is a gate-controlled channel potential that satisfies the source and drain boundary conditions. Verified by...

  15. Support for Cadence Tools

    Q&A|Closed | Responses: 0

    Hi,

    First of all, I am really thankful for the working model of III-IV Tunnel FET Model. I have used VerilogA model files with Cadence Tools and they are working fine. Is it...

    https://nanohub.org/answers/question/1640

  16. VINUTH NAGENDRA

    https://nanohub.org/members/134917

  17. Inter-band Tunnel Transistors: Opportunities and Challenges

    30 Oct 2015 | | Contributor(s):: Suman Datta

    In this talk, we will review progress in Tunnel FETs and also analyze primary roadblocks in the path towards achieving steep switching performance in III-V HTFET.

  18. Design and simulation of GaSb/InAs 2D Transmission enhanced TFET

    10 Oct 2015 | | Contributor(s):: Pengyu Long, Evan Michael Wilson, Jun Huang, mark rodwell, Gerhard Klimeck, Michael Povolotskyi

    IWCE 2015 presentation.  Abstract and more information to be added at a later date.

  19. Universal TFET model

    23 Jan 2015 | Compact Models | Contributor(s):

    By Hao Lu1, Trond Ytterdal2, Alan Seabaugh1

    1. University of Notre Dame 2. Norwegian University of Science and Technology

    A universal TFET compact model implemented in verilog-A

    https://nanohub.org/publications/31/?v=1

  20. raja j

    https://nanohub.org/members/113606