Tags: VLSI design

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  1. Bikash Poudel

    https://nanohub.org/members/182903

  2. Nikhil Chand Kashyap Chitta

    https://nanohub.org/members/155131

  3. Navid Mohammad Imran

    https://nanohub.org/members/135563

  4. Sukanya suhas Chavan

    https://nanohub.org/members/131715

  5. shreyas venkatesh kulkarni

    https://nanohub.org/members/131400

  6. Bipin Chandran

    https://nanohub.org/members/123298

  7. Baihua Xie

    https://nanohub.org/members/117112

  8. Toahera Abdullah

    https://nanohub.org/members/94435

  9. MUHAMMAD JOHIRUL ISLAM

    https://nanohub.org/members/87722

  10. Atul Kumar Singh

    https://nanohub.org/members/84354

  11. VIKASH SHARMA

    https://nanohub.org/members/82172

  12. Souvik Mukherjee

    I am Souvik Mukherjee B.Tech in Electronics & Communication Engineering [2008 - 2012], RCCIIT, West Bengal University of Technology, India, born on October 13, 1989 from West Bengal,...

    https://nanohub.org/members/68222

  13. Sabbir Ebna Razzaque

    https://nanohub.org/members/67938

  14. Yosef Borga

    Attending North Carolina A&T State University.

    https://nanohub.org/members/67190

  15. Abishek Ramdas

    Masters student majoring in VLSI with interest in mathematical physics.

    https://nanohub.org/members/62582

  16. K. R. Kashwan

    https://nanohub.org/members/61340

  17. md abdul haleem bahadur

    https://nanohub.org/members/55885

  18. NanoV: Nanowire-based VLSI Design

    08 Sep 2010 | | Contributor(s):: muzaffer simsir

    In the coming decade, CMOS technology is expected to approach its scaling limitations. Among the proposed nanotechnologies, nanowires have the edge in the size of circuits and logic arrays that have already been fabricated and experimentally evaluated. For this technology, logic-level design...