Last modified 6 years ago Last modified on 04/08/08 18:25:44
  • New features for plot - Threshold voltage and DIBL (Drain Induced Barrier Lowering) = del Vth / del Vd - refer to the attached image file or click the following link.

Threshold voltage -


  • When database for example is loading to the rappture, the messages ("running simulation") will not be shown but the "Retrieving database.." is shown and the input parameters for the example output is shown as in the picture attatched.(or click the following link)

  • 3D simulation for FinFET with poly or metal gate has been run without any critical errors.
  • Comparison with Nanowire - nanowire of diameter 7nm, 10nm, 15nm

  • Comparison with Nanomos - finFET of width 15nm, 20nm

  • First time user guide is updated.