Wish List - III-V Tunnel FET Model: Wish #694

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Geoffrey Coram

Remove analysis() calls; support more than "dc" and "tran"

The Verilog-A code uses the analysis() function, which is on the list of forbidden functions for compact models in most papers on Verilog-A compact modeling.

In particular, the code has

if(analysis("dc")) begin
    I(d,s) <+ 1*Ids*W;
end
else begin
  if(analysis("tran")) begin

so, if you're doing anything but "dc" or "tran" this model will do nothing: ac, noise, pss, ...

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