Summary

The first step is the variation-aware PDK development, as described in the introduction, and summarized in the figure below.

User-provided Inputs

The following user-provided inputs are required to generate variation-aware models for functional yield, timing, power, and noise.

Compact model

SPICE-compatible CNFET device model.

Experimentally-measured variations

Experimentally measured distributions for CNT-CNT spacing variations, CNT type variations (s-CNT: semiconducting CNT, m-CNT: metallic CNT), and CNT diameter variations. For CNT-CNT spacing variations: >100 experimentally measured CNT-CNT spacing values; for CNT type variations: CNT type (m-CNT/s-CNT) for >100 single-CNT devices. Scripts to analyze the impact of CNT variations on CNFET performance metrics (ION, IOFF, sub-threshold slope, threshold voltage, etc.): given user-specified distributions of CNT variations (e.g., the experimentally measured distributions of CNT variations, such as CNT-CNT spacing variations and CNT type variations), and given additional user-specified parameters (e.g., CNFET width), this script automatically: generates SPICE input files, invokes SPICE, and then analyzes the SPICE output to analyze the impact of CNT variations on CNFET device performance variations. Example inputs and their corresponding outputs are also provided. A description of how to modify the scripts for designers using a different compact device model (e.g., based on 2-D materials or III-V FETs) is also provided.

System blocks

For example, a Si-CMOS-based standard cell library (e.g., the 15nm Nangate Open Cell Library), which serves as a template so that each FET (e.g., Si-CMOS MOSFET) can be replaced with a CNFET, to enable timing/power characterization for each CNFET-based standard library cell. Required inputs also include (for each standard library cell): a SPICE netlist, parasitic information (e.g., wire parasitics), layouts, I/O pin sensitivity information, I/O locations.

Generated Outputs

For each standard library cell, NDK automatically generates SPICE decks for timing/power/noise/yield analysis (given distributions of CNT variations, e.g., the experimentally measured distributions), invokes SPICE, then characterizes the timing/power/noise/yield performance in both the nominal case (no variations), and in the case of CNT variations. Example inputs (see above) and their corresponding outputs (see below) are also provided. A description of how to modify the scripts for designers using a different compact device model (e.g., based on 2-D materials or III-V FETs) is also provided.

Variation-aware models: timing, power, noise

Timing/power LIBERTY file for standard cell library timing/power characterization (for use with commercially available synthesis tools), as well as variation-aware models for timing/power/noise/yield, which are used to analyze the system-level impact of CNT variations for large circuit modules (e.g., from the OpenSparc T2 SoC).

External Tools

The following tools are required to generate the variation-aware PDK