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9nm GaSb-InAs TFET Models with Doped Source Underlap for Circuit Simulations
03 Dec 2014 | Downloads | Contributor(s): Ankit Sharma, Arun Goud Akkala, Kaushik Roy
7nm Si FinFET Models with Symmetric and Asymmetric Underlap for Circuit Simulations
23 Aug 2013 | Downloads | Contributor(s): Arun Goud Akkala, Sumeet Kumar Gupta, Sri Harsha Choday, Kaushik Roy