7nm Si FinFET Models with Symmetric and Asymmetric Underlap for Circuit Simulations
23 Aug 2013 | Downloads | Contributor(s): Arun Goud Akkala, Sumeet Kumar Gupta, Sri Harsha Choday, Kaushik Roy
This tarball contains Verilog-A compact lookup table models for 7nm channel length Si FinFET with different underlaps which can be used in HSPICE netlists for circuit simulations. Device simulation data for constructing the lookup table model was generated using NEMO5 atomistic tight binding transport simulator (also available on Nanohub.org).
Usage notes, example input netlists and full device description are also included.
* r2.1- Updated on 2014/08/11