Reed-Muller Reversible Logic Synthesizer (RMRLS) 0.2
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Downloads | 04 Jan 2008 | Contributor(s): James Donald, Pallav Gupta
Reed-Muller Reversible Logic Synthesis tool (a.k.a. RELOS) is a tool for the synthesis of reversible functions based on positive-polarity Reed-Muller expressions. The second release of RMRLS features reversible logic synthesis with SWAP, Fredkin, and Peres gates. This work was done under the...
RMRLS 0.2
Downloads | 27 Dec 2007 | Contributor(s): James Donald, Pallav Gupta
Reed-Muller Reversible Logic Synthesis tool (aka RELOS) is a tool for the synthesis of reversible functions based on positive-polarity Reed-Muller expressions. The second release of RMRLS a.k.a. RELOS features reversible logic synthesis with SWAP, Fredkin, and Peres gates.This work was done under...
ThrEshold Logic Synthesizer (TELS) and Majority Logic Synthezier (MALS)
Downloads | 09 Oct 2007 | Contributor(s): Pallav Gupta
TELS and MALS are threshold and majority/minority logic synthesis tools that were developed by Rui Zhang and Pallav Gupta under the supervision of Prof. Niraj K. Jha of Princeton University. Dr. Lin Zhong, of Rice University, was also a contributor.Both of these tools have been integrated into...
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