Publications: Compact Models

  1. Multi-walled/Single-walled Carbon Nanotube (MWCNT/SWCNT) Interconnect Lumped Compact Model Considering Defects, Contact resistance and Doping impact

    2018-07-18 16:10:04 | Contributor(s): Rongmei Chen, Jie LIANG, Jaehyun Lee, Vihar Georgiev, Aida Todri | doi:10.4231/D3183448N

    In this project, we present SWCNT and MWCNT interconnect compact models. These models consider the impact of CNT defects, the chirality and contact resistance between CNT-electrode (Pd) on CNT interconnect performances and power consumption. Variabilities
  2. Compact Model of Dielectric Breakdown in Spin Transfer Torque Magnetic Tunnel Junction

    2018-04-16 17:57:33 | Contributor(s): You Wang, Yue Zhang, Weisheng Zhao, Dafine Ravelosona, Jacques-Olivier Klein, Lirida Naviner, Hao Cai

    Spin Transfer Torque Magnetic Tunnel Junction (STT-MTJ) is a promising candidate for non-volatile memories thanks to its high speed, low power, infinite endurance and easy integration with CMOS circuits.
  3. Compact model for Perpendicular Magnetic Anisotropy Magnetic Tunnel Junction

    2018-04-16 17:57:57 | Contributor(s): You WANG, Yue ZHANG, Weisheng Zhao, Jacques-Olivier Klein, Dafiné Ravelosona, Hao Cai, Lirida Naviner

    This STT PMA MTJ model integrates the physical models of static, dynamic behaviors and reliability issues, which can be used to perform more accurate and complex reliability analysis of complex hybrid circuits before fabrication.
  4. A Verilog-A Compact Model for Negative Capacitance FET

    2017-11-09 16:55:37 | Contributor(s): Muhammad Abdul Wahab, Muhammad A. Alam | doi:10.4231/D3QZ22K3Z

    The NC-FET compact model is a semi-physical verilog-A model of the negative capacitance transistor. We developed this self-consistent model with BSIM4/MVS and Landau theory. This model is useful to design NC-FET for high speed and low power...
  5. CNRS - Carbon Nanotube Interconnect RC Model

    2017-11-09 16:25:31 | Contributor(s): Jie LIANG, Aida Todri | doi:10.4231/D3SJ19T14

    This CNT Interconnect Compact Model includes a solid physics understanding and electrical modeling for pristine and doped SWCNT as Interconnect applications. SWCNT resistance and capacitance are modeled in Verilog-A.
  6. Notre Dame TFET Model

    2017-09-01 17:35:14 | Contributor(s): Hao Lu, Trond Ytterdal, Alan Seabaugh | doi:10.4231/D3CF9J852

    Notre Dame TFET compact model version 2.1.0.
  7. JFETIDG Model for Independent Dual-Gate JFETs

    2017-07-27 12:55:51 | Contributor(s): Colin McAndrew, Kejun Xia | doi:10.4231/D3KK94F1N

    JFETIDG is a compact model for independent dual-gate JFETs. It is also applicable to: resistors with metal shields; the drift region of LDMOS transistors; the collector resistance of vertical bipolar transistors; and junctionless MOS transistors.
  8. Purdue Solar Cell Model (PSM) - Perovskite/a-Si (p-i-n)

    2018-04-16 17:56:34 | Contributor(s): Xingshu Sun, Raghu Vamsi Krishna Chavali, Sourabh Dongaonkar, Suhas Venkat Baddela, Mark Lundstrom, Muhammad Ashraful Alam | doi:10.4231/D3862BC8C

    Purdue Solar Cell Model (PSM), previously known as the TAG (technology agnostic) model, is a suite of compact models developed for solar cells of c-Si, a-Si, perovskites, CIGS, CdTe, and HIT. This package is for perovskite and a-Si solar cells.
  9. Purdue Solar Cell Model (PSM) - HIT

    2018-04-16 18:09:10 | Contributor(s): Xingshu Sun, Raghu Vamsi Krishna Chavali, Sourabh Dongaonkar, Suhas Venkat Baddela, Mark Lundstrom, Muhammad Ashraful Alam | doi:10.4231/D3CV4BS80

    Purdue Solar Cell Model (PSM), previously known as the TAG (technology agnostic) model, is a suite of compact models developed for solar cells of c-Si, a-Si, perovskites, CIGS, CdTe, and HIT. This package is for perovskite and a-Si solar cells.
  10. Purdue Solar Cell Model (PSM) - Si

    2018-04-16 18:09:34 | Contributor(s): Mark Lundstrom, Muhammad Ashraful Alam, Raghu Vamsi Krishna Chavali, Sourabh Dongaonkar, Suhas Venkat Baddela, Xingshu Sun | doi:10.4231/D3HM52M18

    Purdue Solar Cell Model (PSM), previously known as the TAG (technology agnostic) model, is a suite of compact models developed for solar cells of c-Si, a-Si, perovskites, CIGS, CdTe, and HIT. This package is for c-Si solar cells.
  11. Purdue Solar Cell Model (PSM) - CIGS/CdTe

    2018-04-16 18:09:56 | Contributor(s): Xingshu Sun, Sourabh Dongaonkar, Raghu Vamsi Krishna Chavali, Suhas Venkat Baddela, Mark Lundstrom, Muhammad Ashraful Alam | doi:10.4231/D3NC5SD6H

    Purdue Solar Cell Model (PSM), previously known as the TAG (technology agnostic) model, is a suite of compact models developed for solar cells of c-Si, a-Si, perovskites, CIGS, CdTe, and HIT. This package is for CIGS/CdTe.
  12. MIT TFET compact model including the impacts of non-idealities

    2017-05-08 02:34:24 | Contributor(s): Redwan Noor Sajjad, Ujwal Radhakrishna, Dimitri Antoniadis | doi:10.4231/D3XW47X6W

    We present a compact model for tunnel FET that for the first time fits experimental transfer and output characteristics including the impact of non-idealities such as trap assisted tunneling and intrinsic band steepness.
  13. UCSB Graphene Nanoribbon Interconnect Compact Model

    2017-05-03 21:16:20 | Contributor(s): Junkai Jiang, Kaustav Banerjee, Wei Cao | doi:10.4231/D3NK3663N

    This model describes the circuit-level behavior of the (intercalation) doped GNR interconnect, and is compatible with both DC and transient SPICE simulations.
  14. Optical Ring Modulator with MIT Virtual Source ModSpec Compact Model

    2017-05-03 21:19:10 | Contributor(s): Lily Weng | doi:10.4231/D3PK0732D

    In this release, we apply MIT virtual source model in the driver circuits of Optical Ring Modulators.
  15. Thermoelectric Device Compact Model

    2017-03-27 13:46:21 | Contributor(s): Xufeng Wang, Kyle Conrad, Jesse Maassen, Mark Lundstrom | doi:10.4231/D3PN8XG7R

    The NEEDS thermoelectric compact model describes a homogeneous segment of thermoelectric material and serves as a basic building block for complex electrothermal system.
  16. MIT Virtual Source Negative Capacitance (MVSNC) model

    2017-03-07 01:06:52 | Contributor(s): Ujwal Radhakrishna, Asif Islam Khan, Sayeef Salahuddin, Dimitri Antoniadis | doi:10.4231/D3K649T9T

    MIT Virtual Source Negative FET (MVSNC) model is a compact model for negative capacitance transistors that use a FE-oxide in the gate stack to achieve internal voltage amplification and steep subthreshold swing.
  17. UARK SiC Power MOSFET Model

    2017-02-23 14:45:14 | Contributor(s): Mihir Mudholkar, Shamim Ahmed, Ramchandra Kotecha, Ty McNutt, Arman Ur Rashid, Tom Vrotsos, Alan Mantooth | doi:10.4231/D3QF8JK88

    A compact model for SiC Power MOSFETs is presented. The model features a physical description of the channel current and internal capacitances and has been validated for dc, CV, and switching characteristics with measured data from C2M0025120D.
  18. nMOSFET RF and noise model on standard 45nm SOI technology

    2017-01-05 16:57:48 | Contributor(s): Yanfei Shen, Saeed Mohammadi | doi:10.4231/D3833N04K

    A compact scalable model suitable for predicting high frequency noise and nonlinear behavior of N-type Metal Oxide Semiconductor (NMOS) transistors is presented.
  19. Optical Ring Modulator ModSpec Compact Model

    2017-01-05 16:54:03 | Contributor(s): Lily Weng, Tianshi Wang | doi:10.4231/D31N7XN9P

    The optical ring modulator presented here is a vertical junction resonant microring/disk modulator which can achieve high modulation speed, lower power consumption and compact size. A Matlab-based ModSpec compact model is developed and simulated.
  20. Flexible Transition Metal Dichalcogenide Field-Effect Transistor (TMDFET) Model

    2016-05-04 03:37:43 | Contributor(s): Morteza Gholipour, Deming Chen | doi:10.4231/D3TM72243

    Verilog-A model of flexible transition metal dichalcogenide field-effect transistors (TMDFETs), considering effects when scaling the transistor size down to the 16-nm technology node.