05 Ferroelectric Devices for Compute-in-Memory: Array-Level Operations
Ferroelectric Devices for Compute-in-Memory: Array-Level Operations
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1. Ferroelectric Devices for Comp…
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2. Hardware Accelerators for AI
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3. A Shift in Computing Paradigm …
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4. Crossbar Architecture for Acce…
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5. Engineering Resistive Synaptic…
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6. Wish-list for Resistive Synapt…
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7. Questions?
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8. Ferroelectric Transistor (FeFE…
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9. Symmetric and Fast Weight Upda…
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10. Motivation for 2T-1FeFET Synap…
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11. Hybrid Precision for Training …
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12. 2T-1FeFET Weight Cell Design
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13. Multilevel Programming in FeFE…
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14. FeFET Compact Model
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15. Demonstration of 2-bit MSBs + …
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16. Demonstration of 2-bit MSBs + …
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17. Gate Voltage Leakage Analysis
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18. Evaluation on CIFAR-10 Dataset
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19. Questions?
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20. Individual Cell Program/Erase …
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21. Device Characterization – Dr…
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22. Why FDSOI Performs Better in D…
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23. Device Characterization – Pr…
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24. Device Characterization – In…
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25. Device Characterization – In…
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26. A Vision to Future 3D Vertical…
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27. Summary
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28. Acknowledgement
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