Exploring CMOS-Nano Hybrid Technology in Three Dimensions
CMOS-nano hybrid technology incorporate the advantages of both traditional CMOS and novel nanowire/nanotube structures, which will enhance future IC performances and create long-term breakthroughs. The CMOS-nano hybrid IC can be efficiently …
| Abstract | The CMOS-nano hybrid technology tries to utilize the advantages of both traditional CMOS and novel nanowire/nanotube structures, which will enhance IC performances in the near future and create breakthroughs in the long run. The CMOS-nano hybrid IC can be efficiently fabricated using the 3D integration approach. This talk will present the recent progress in designing and building such 3D hybrid ICs for FPGA and neuromorphic network applications. |
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| Bio | 
Wei Wang received his Ph. D degree from Concordia University, Montreal, QC, Canada (Electrical and Computer Engineering) in 2002. From 2002 to 2004, he was an Assistant professor in the Department of Electrical and Computer Engineering, the University of Western Ontario, London, ON, Canada. From 2005 to 2007, he was an assistant professor in the Department of Electrical and Computer Engineering, Purdue University Indianapolis. In December 2007, he joined CNSE of UAlbany as a senior research scientist and assistant professor. His main research interests are nanoelectronics, CMOS-nano hybrid circuit, 3D IC, ASIC and FPGA design. His is the inventor of 3D CMOL, nFPGA and rFPGA. He has over 90 journal and conference papers and three US patents. He received New Opportunities Fund Award from Canadian Foundation of Innovation in 2004, IUPUI Research Initiative Award and CCECE Best Paper Award in 2005. |
| Sponsored by | NCN@Purdue Student Leadership Team, Network for Computational Nanotechnology, The Institute for Nanoelectronics and Computing |
| Cite this work | Researchers should cite this work as follows: |
| Time | 02:30 PM, March 19, 2008 |
| Location | EE 317, Purdue University, West Lafayette, IN |
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