Effect of the High-k Dielectric/Semiconductor Interface on Electronic Properties in Ultra-thin Channels

By Daniel A. Valencia-Hoyos1, Evan Michael Wilson1, mark rodwell2, Gerhard Klimeck1, Michael Povolotskyi1

1. Purdue University 2. Electrical and Computer Engineering, UCSB, Santa Barbara, CA

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Abstract

IWCE 2015 presentation.  Abstract and more information to be added at a later date.

As logic devices continue to downscale, an increasing fraction of the channel atoms are in close contact with oxide atoms of the gate. These surface atoms experience a chemical environment that is distinct from the bulk-like environment found in thicker channels. Using the non- orthogonal tight-binding method Extended Huckel Theory (EHT), III-IV/High-k dielectric interfaces are constructed and electronic structure in the two transverse directions in the plane of the interface is calculated.

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Cite this work

Researchers should cite this work as follows:

  • Valencia-Hoyos, Daniel A., "Effect of the High-k Dielectric/Semiconductor Interface on Electronic Properties in Ultra-thin Channels," in Computational Electronics (IWCE) 2015 International Workshop on, DOI: Not available in IEEE Xplore digital library. Full Website Here

  • Daniel A. Valencia-Hoyos; Evan Michael Wilson; mark rodwell; Gerhard Klimeck; Michael Povolotskyi (2015), "Effect of the High-k Dielectric/Semiconductor Interface on Electronic Properties in Ultra-thin Channels," http://nanohub.org/resources/22875.

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Location

North Ballroom, PMU, Purdue University, West Lafayette, IN

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