Support

Support Options

Submit a Support Ticket

 

See also

No results found.

Category

Downloads

Published on

Abstract

In the coming decade, CMOS technology is expected to approach its scaling limitations. Among the proposed nanotechnologies, nanowires have the edge in the size of circuits and logic arrays that have already been fabricated and experimentally evaluated. For this technology, logic-level design methodologies are being developed. The time has now come to develop automated tools for implementing VLSI designs using nanowires. In this project, we present a design automation tool, called NanoV, to fulfill this need for nanowires. It is a complete logic-to-layout tool with built-in defect-aware steps since the defect levels in nanotechnologies are expected to be relatively high (between 1 to 10%). We calculate area/delay/power results for given circuit definitions implemented using our tool.

Publications

M. O. Simsir, Niraj K. Jha, "NanoV: Nanowire-based VLSI Design", in Proc. Int. Symp. Nanoscale Architectures, June 2010, pp. 53-58

Cite this work

Researchers should cite this work as follows:

  • Please refer to our publication.
  • muzaffer simsir (2010), "NanoV: Nanowire-based VLSI Design," http://nanohub.org/resources/9629.

    BibTex | EndNote

Tags

No classroom usage data was found. You may need to enable JavaScript to view this data.

nanoHUB.org, a resource for nanoscience and nanotechnology, is supported by the National Science Foundation and other funding agencies. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.