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2011 NCN@Purdue Summer School: Electronics from the Bottom Up
Workshops | 20 Jul 2011
click on image for larger versionAlumni Discussion Group: LinkedIn
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A UCSD analytic TFET model
Downloads | 18 Dec 2015 | Contributor(s):: Jianzhi Wu, Yuan Taur
A continuous, analytic I-V model is developed for double-gate and nanowire tunnel FETs with 3D density of states, including depletion in the source. At the core of the model is a gate-controlled channel potential that satisfies the source and drain boundary conditions. Verified by...
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ABACUS - Assembly of Basic Applications for Coordinated Understanding of Semiconductors
Tools | 16 Jul 2008 | Contributor(s):: Xufeng Wang, Daniel Mejia, Dragica Vasileska, Gerhard Klimeck
One-stop-shop for teaching semiconductor devices
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Atomistic Modeling of Nano Devices: From Qubits to Transistors
Online Presentations | 12 Apr 2016 | Contributor(s):: Rajib Rahman
In this talk, I will describe such a framework that can capture complex interactions ranging from exchange and spin-orbit-valley coupling in spin qubits to non-equilibrium charge transport in tunneling transistors. I will show how atomistic full configuration interaction calculations of exchange...
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Atomistic Simulations of Reliability
Teaching Materials | 01 Jul 2010 | Contributor(s):: Dragica Vasileska
Discrete impurity effects in terms of their statistical variations in number and position in the inversion and depletion region of a MOSFET, as the gate length is aggressively scaled, have recently been researched as a major cause of reliability degradation observed in intra-die and die-to-die...
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BJT Lab
Tools | 06 Feb 2008 | Contributor(s):: Saumitra Raj Mehrotra, Abhijeet Paul, Gerhard Klimeck, Dragica Vasileska, Gloria Wahyu Budiman
This tool simulates a Bipolar Junction Transistor (BJT) using a 2D mesh. Powered by PADRE.
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Chapter 1: A Primer MOSCap Tool on nanoHUB.org
Papers | 19 Mar 2020 | Contributor(s):: Abdussamad Ahmed Muntahi, Shaikh S. Ahmed
The primary reason to study MOS (metal-oxide-semiconductor) capacitors is to understand the principle of operation as well as become familiar with some of the routinely used characterization techniques for MOS field effect transistors (MOSFETs). The MOSCap tool on nanoHUB.org simulates the...
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Chapter 1: A Primer on the MOSFet Simulator on nanoHUB.org
Papers | 19 Mar 2020 | Contributor(s):: Abdussamad Ahmed Muntahi, Dragica Vasileska, Shaikh S. Ahmed
The MOSFet simulator on nanoHUB.org (http://nanohub.org/resources/mosfet) simulates the equilibrium electrostatics and non-equilibrium current-voltage (I-V) characteristics of i) bulk, ii) dual-gate, and iii) SOI based field effect transistors. In this chapter, we will describe: i) the structure...
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Computational and Experimental Study of Transport in Advanced Silicon Devices
Papers | 28 Jun 2013 | Contributor(s):: Farzin Assad
In this thesis, we study electron transport in advanced silicon devices by focusing on the two most important classes of devices: the bipolar junction transistor (BJT) and the MOSFET. In regards to the BJT, we will compare and assess the solutions of a physically detailed microscopic model to...
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Device Parameters Extraction Within Silvaco Simulation Software
Teaching Materials | 30 Jul 2011 | Contributor(s):: Dragica Vasileska
This set of slides explains the extract statements within SILVACO simulation software.
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Device Physics Studies of III-V and Silicon MOSFETS for Digital Logic
Papers | 28 Jun 2013 | Contributor(s):: Himadri Pal
III-V's are currently gaining a lot of attraction as possible MOSFET channel materials due to their high intrinsic mobility. Several challenges, however, need to be overcome before III-V's can replace silicon (Si) in extremely scaled devices. The effect of low density-of-states of III-V materials...
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Direct Solution of the Boltzmann Transport Equation in Nanoscale Si Devices
Papers | 28 Jun 2013 | Contributor(s):: Kausar Banoo
Predictive semiconductor device simulation faces a challenge these days. As devices are scaled to nanoscale lengths, the collision-dominated transport equations used in current device simulators can no longer be applied. On the other hand, the use of a better, more accurate Boltzmann Transport...
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ECE 612 Lecture 23: RF CMOS
Online Presentations | 02 Dec 2008 | Contributor(s):: Mark Lundstrom
Outline: 1) Introduction,2) Small signal model,3) Transconductance,4) Self-gain,5) Gain bandwidth product,6) Unity power gain,7) Noise, mismatch, linearity…,8) Examples
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Electron Density in a Nanowire
Animations | 30 Jan 2011 | Contributor(s):: Gerhard Klimeck, Saumitra Raj Mehrotra
Electron Density in a circular Silicon nanowire transistor.
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Electron Transport in Schottky Barrier CNTFETs
Papers | 24 Oct 2017 | Contributor(s):: Igor Bejenari
This resource has been removed at the request of the author.A given review describes models based on Wentzel-Kramers-Brillouin approximation, which are used to obtain I-V characteristics for ballistic CNTFETs with Schottky-Barrier (SB) contacts. The SB is supposed to be an exponentially...
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Electron-Electron Interactions
Teaching Materials | 20 Jun 2011 | Contributor(s):: Dragica Vasileska
This set of slides describes the electron-electron interactions scattering rates calculations as it occurs in bulk materials, low-dimensional structures and semiconductor devices.
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From density functional theory to defect level in silicon: Does the “band gap problem” matter?
Online Presentations | 01 Oct 2008 | Contributor(s):: Peter A. Schultz
Modeling the electrical effects of radiation damage in semiconductor devices requires a detailed description of the properties of point defects generated during and subsequent to irradiation. Such modeling requires physical parameters, such as defect electronic levels, to describe carrier...
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Guidelines for Writing NEEDS-certified Verilog-A Compact Models
Online Presentations | 19 Jun 2013 | Contributor(s):: Tianshi Wang, Jaijeet Roychowdhury
This talk contains a brief introduction to Verilog-A and suggests some initial guidelines for writing Verilog-A versions of NEEDS models. For more about the history of Verilog-A and additional guidelines for writing Verilog-A models, see the presentation by Drs. Geoffrey Coram and Colin McAndrew.
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III-V Nanoscale MOSFETS: Physics, Modeling, and Design
Papers | 28 Jun 2013 | Contributor(s):: Yang Liu
As predicted by the International Roadmap for Semiconductors (ITRS), power consumption has been the bottleneck for future silicon CMOS technology scaling. To circumvent this limit, researchers are investigating alternative structures and materials, among which III-V compound semiconductor-based...
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Illinois ECE 440 Solid State Electronic Devices, Lecture 1 Introduction
Online Presentations | 26 Nov 2008 | Contributor(s):: Eric Pop
Introduction to Solid State Electronic Devices