JFETlab: An Online Simulation Tool for Double Gate long channel Symmetrical Si and 4H-SiC JFETs

By Nikolaos Makris1, Matthias Bucher1, Farzan Jazaeri2

1. School of Electrical and Computer Engineering (ECE) of the Technical University of Crete (TUC) 2. EPFL

JFETlab is a simulation tool of static and dynamic electrical characteristics ( I-V, G-V, C-V ) of Si and 4H-SiC Junction Field Effect Transistors (JFETs) using temperature and channel concentration depedent material models.

Launch Tool

You must login before you can run this tool.

Version 1.2 - published on 07 Jun 2021

doi:10.21981/2JXY-BK35 cite this

This tool is closed source.

View All Supporting Documents

Usage

World usage

Location of all "JFETlab: An Online Simulation Tool for Double Gate long channel Symmetrical Si and 4H-SiC JFETs" Users Since Its Posting

Cumulative Simulation Users

316

9 11 13 17 25 29 30 33 37 45 46 47 52 52 55 64 68 74 83 94 105 115 123 130 143 148 161 179 192 221 244 258 267 275 275 281 285 296 304 316

Users By Organization Type
Type Users
Unidentified 304 (96.2%)
Educational - University 12 (3.8%)
Users by Country of Residence
Country Users
us UNITED STATES 3 (25%)
in INDIA 2 (16.67%)
cn CHINA 2 (16.67%)
my MALAYSIA 1 (8.33%)
eg EGYPT 1 (8.33%)
gb UNITED KINGDOM 1 (8.33%)
vn VIET NAM 1 (8.33%)
id INDONESIA 1 (8.33%)

Simulation Runs

2,406

73 95 737 758 1048 1182 1213 1221 1228 1265 1266 1267 1326 1330 1334 1351 1357 1376 1392 1407 1442 1577 1601 1619 1640 1664 1765 1788 1903 1983 2073 2104 2116 2130 2130 2161 2166 2213 2239 2406
Overview
Average Total
Wall Clock Time 39.95 minutes 98.34 days
CPU time 0.81 seconds 48.14 minutes
Interaction Time 9.34 minutes 22.98 days