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NUCL 200 Lecture 18: Primary and Secondary System of a Pressurized Water Reactor
Online Presentations | 10 Oct 2024 | Contributor(s):: Allen Garner
Topics:Function of reactor coolant pumpsFucntion and operation of the pressurizerTwo systems within the secondaryOverview and diagram of the secondary systemFunction and operation of the condenser
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Silvaco TCAD (High Memory)
Tools | 10 Oct 2024 | Contributor(s):: Gerhard Klimeck, Steven Clark, Alejandro Strachan, Eric Guichard, Thomas Jokinen
SILVACO Semiconductor Process and Device Simulation for Educational Purposes Only, see License below.
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Large Language models for Quantum Espresso
Tools | 09 Oct 2024 | Contributor(s):: Juan Carlos Verduzco Gastelum, Alejandro Strachan
Large Language models for Quantum Espresso
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NUCL 200 Lecture 19: Nuclear Reactor Fuels
Online Presentations | 08 Oct 2024 | Contributor(s):: Allen Garner
Topics:Breeder reactionsConversion RatioBreeding ratioLinear doubling timeExponential doubling timeBurnup and specific burnupPractice problem
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M29 - Hardware Security of Drones
Online Presentations | 08 Oct 2024 | Contributor(s):: Md Tauhindur Rhaman, Sadik Awal
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M28 - Introduction to UAVs
Online Presentations | 08 Oct 2024 | Contributor(s):: Md Tauhindur Rhaman, Sadik Awal
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M31 - Digital Twin of UAV Hardware
Online Presentations | 08 Oct 2024 | Contributor(s):: Md Tauhindur Rhaman, Sadik Awal
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M30 - UAV Cybersecurity
Online Presentations | 08 Oct 2024 | Contributor(s):: Md Tauhindur Rhaman, Sadik Awal
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M52 - RO PUF Implementation II
Online Presentations | 08 Oct 2024 | Contributor(s):: Jim Plusquellic
Learning Objectives:The primary learning objective of this module is for trainees to be exposed to the process of evaluating important properties of a PUF architecture, using the RO PUF implementation as an example. We first determine an optimal runtime for testing each of the ROs in the array...
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M37 - RO PUF Implementation I
Online Presentations | 08 Oct 2024 | Contributor(s):: Jim Plusquellic
Learning Objectives:The primary learning objective of this module is to demonstrate to trainees to the process of building an RO PUF architecture on an FPGA, and to expose them to the anomalies that present themselves when attempting to build a PUF that is capable of producing response bitstrings...
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M36 - PUF Architectures I
Online Presentations | 08 Oct 2024 | Contributor(s):: Jim Plusquellic
Learning Objectives:The primary learning objective of this module is for trainees to be exposed to the different classes of PUF architectures, and to learn about the details of the originally proposed PUF architectures, namely, the Arbiter and RO PUFs. The benefits and vulnerabilities of the...
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M35 - PUF Classes and Applications
Online Presentations | 08 Oct 2024 | Contributor(s):: Jim Plusquellic
Learning Objectives:The primary learning objective of this module is for trainees to learn the differences between Strong and Weak PUF using example PUF architectures. Instruction is then provided on PUF usage scenarios, including a non-security-related role of device identification, and...
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NUCL 200 Lecture 17: Neutron Life Cycle and Pressurized Water Reactors
Online Presentations | 07 Oct 2024 | Contributor(s):: Allen Garner
Topics:Neutron life cycle6-factor formula4-factor formulaPrimary system of a pressurized water reactorCalculation of reactor powerHeat transfer in the steam generator
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Enhance Electrical and Computer Engineering Undergraduate Classes with Verilog Projects
Courses | 07 Oct 2024 | Contributor(s):: Suxia Cui
This project introduces a sequence of digital design projects utilizing Verilog and Field-Programmable Gate Arrays (FPGAs). Enhancing students’ proficiency in Verilog is expected to significantly improve their capabilities in chip design, aligning their skills with industry standards and...
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Digital Design Laboratory Lab 4: JK Flip-Flop
Teaching Materials | 07 Oct 2024 | Contributor(s):: Suxia Cui
The learning goal is to bridge the gap between theoretical knowledge of digital logic design and its practical application on FPGA hardware, providing real-world experience with both design and hardware verification of JK Flip-Flop.
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Digital Design Laboratory Lab 3: D Flip-Flop
Teaching Materials | 07 Oct 2024 | Contributor(s):: Suxia Cui
The objective of this experiment is to understand the operation of the D flip-flop and to observe its behavior under different clock and input conditions. The D flip-flop is used in digital circuits for data storage, synchronization, and edge-triggered events.
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Digital Design Laboratory Lab 2: Adder-Subtractor
Teaching Materials | 07 Oct 2024 | Contributor(s):: Suxia Cui
Goal:To understand the working principles of digital adders and subtractors.To design a 1-bit half adder-subtractor circuit using Verilog.To implement and test the adder-subtractor design on an FPGA board.To understand the process of synthesizing, simulating, and debugging a digital circuitusing...
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Digital Design Laboratory Lab 1: Decoder
Teaching Materials | 07 Oct 2024 | Contributor(s):: Suxia Cui
Gain hands-on experience in designing, implementing, and testing digital logic circuits like decoders on hardware.
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Digital Design Laboratory: Software Installation
Teaching Materials | 07 Oct 2024 | Contributor(s):: Suxia Cui
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Digital Design Laboratory: Hardware Introduction
Teaching Materials | 07 Oct 2024 | Contributor(s):: Suxia Cui