This presentation is part of 2015 IEDM tutorials
The industry march along Moore's Law continues and new semiconductor nodes at 7 and beyond will certainly happen. However, many device, material, and economical challenges remain. This tutorial will target understanding key device concepts for 7nm node and beyond.
The tutorial will start with a brief review of state of the art for logic technologies followed by the likely metrics the industry will use to guide the 7nm and beyond device and material options. The next section of the talk will give a tutorial on many of the key device concepts that will shape the value proposition of 7nm and beyond.
1. Introduction to state-of-the-art for logic devices
2. Metrics for logic device going forward
3. Deeper look at some advanced device concepts
- Transistor variation/random doping effect
- Strain Si, Ge, and III-V channels
- Quantum confinement
- Drive current and relation to mobility, velocity saturation, and density of states
- External resistance
- Sub fin doping and gate all around devices
4. Conclusion: How does the roadmap evolve?
Dr. Thompson is a Professor of Electrical Engineering at the University of Florida focusing on advanced transistor technologies. Dr. Thompson worked on low power transistors for IOT applications at SuVolta. Dr. Thompson was also an Intel Fellow, Director of Logic Technology and responsible for next generation process integration, technology yield and transistor design at Intel. Dr. Thompson and his co-workers were the first to publish at the International Electron Device Meeting (IEDM) in 2002 on a 90nm logic technology which introduced high levels strain for significant mobility enhancement using SiGe. Dr. Thompson was elected an IEEE Fellow for his contributions on submicron and nanoscale MOSFETs.
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