2014 NCN-NEEDS Summer School: Spintronics - Science, Circuits, and Systems
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SPICE Models for Magnetic Tunnel Junctions Based on Monodomain Approximation
21 Aug 2013 | Downloads | Contributor(s): Xuanyao Fong, Sri Harsha Choday, Panagopoulos Georgios, Charles Augustine, Kaushik Roy
Models for simulating a magnetic tunnel junction in HSPICE. The usage description is included in the "USAGE" text file included in the archive. The libraries are encrypted and have been tested in HSPICE-G-2012.06, HSPICE-E-2010.12-SP2 and HSPICE-D-2010.03-SP1. The archives are named...
7nm Si FinFET Models with Symmetric and Asymmetric Underlap for Circuit Simulations
23 Aug 2013 | Downloads | Contributor(s): Arun Goud Akkala, Sumeet Kumar Gupta, Sri Harsha Choday, Kaushik Roy
This tarball contains Verilog-A compact lookup table models for 7nm channel length Si FinFET with different underlaps which can be used in HSPICE netlists for circuit simulations. Device simulation data for constructing the lookup table model was generated using NEMO5 atomistic...
Design of CMOS Circuits in the Nanometer Regime: Leakage Tolerance
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28 Nov 2006 | Online Presentations | Contributor(s): Kaushik Roy
The scaling of technology has produced exponential growth in transistor development and computing power in the last few decades, but scaling still presents several challenges. These two lectures will cover device aware CMOS design to address power, reliability, and process variations in scaled...
Design in the Nanometer Regime: Process Variation
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Scaling of technology over the last few decades has produced an exponential growth in computing power of integrated circuits and an unprecedented number of transistors integrated into a single. However, scaling is facing several problems — severe short channel effects, exponential increase in...
Magnetic Tunnel Junction (MTJ) as Stochastic Neurons and Synapses: Stochastic Binary Neural Networks, Bayesian Inferencing, Optimization Problems
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26 Oct 2018 | Online Presentations | Contributor(s): Abhronil Sengupta, Kaushik Roy
In this presentation, we provide a multi-disciplinary perspective across the stack of devices, circuits, and algorithms to illustrate how the stochastic switching dynamics of spintronic devices in the presence of thermal noise can provide a direct mapping to the units of such computing...
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Purdue Nanoelectronics Research Laboratory Magnetic Tunnel Junction Model
23 Oct 2014 | Contributor(s): Xuanyao Fong, Sri Harsha Choday, Panagopoulos Georgios, Charles Augustine, Kaushik Roy | doi:10.4231/D33R0PV04
This is the Verilog-A model of the magnetic tunnel junction developed by the Nanoelectronics Research Laboratory at Purdue University.