Profile

• Website

  https://www.eng.auburn.edu/users/uguin/index.html

  
  
• Telephone

  13348441835

  
  
• ORCID

  0000-0002-4819-8728

  
  
• Google Scholar

  https://scholar.google.com/citations?user=rqpI_MoAAAAJ&hl=en&oi=sra

  
  
• ResearcherID

  (not set)

  
  
• ScopusID

  (not set)

  
  
• ResearchGateID

  (not set)

  
  
• LinkedIn Profile

  https://www.linkedin.com/in/ujjwalguin/

  
  
• Twitter Account

  (not set)

  
  
• Facebook Profile

  (not set)

  
  
• Gender

  Male

  
  
• Disability

  No (none)

  
  
• Reason

  (not set)

  
  
• Interests

  1. blockchain
  2. Counterfeit IC Detection
  3. Cybersecurity
  4. Hardware Security

  
  
• Address

  address1:	200 Broun Hall
  city:	AUBURN
  postal:	36849
  region:	AL
  country:	US

  
  
• Hispanic Heritage

  No (not Hispanic or Latino)

  
  
• Biography

  Ujjwal Guin is currently an Associate Professor at the Department of Electrical and Computer Engineering, Auburn University. He received his Ph.D. degree from the University of Connecticut in 2016. He is actively involved in projects in the fields of Hardware Security and Trust, Supply Chain Security, Cybersecurity, and VLSI Design and Test. He has developed several on-chip structures and techniques to improve the security, trustworthiness, and reliability of integrated circuits. He is a co-author of the book "Counterfeit Integrated Circuits: Detection and Avoidance". He has authored several journal articles and refereed conference papers. His projects are sponsored by the Air Force Office of Scientific Research (AFSOR), United States Secret Service (USSS), National Science Foundation (NSF), Air Force Research Laboratory (AFRL), and Auburn University.
  
  Dr. Guin was actively involved in developing a web-based tool, Counterfeit Defect Coverage Tool (CDC Tool), http://www.sae.org/standardsdev/cdctool/. This tool has been adopted in "AS6171: Test Methods Standard; General Requirements, Suspect/Counterfeit, Electrical, Electronic, and Electromechanical Parts" for the basis of test method selection and evaluation of test effectiveness. He serves on the SAE International G-19A Test Laboratory Standards Development Committee and G-32 Cyber-Physical Systems Security Committee. He currently serves or has served several technical program committees in several reputed conferences, such as DAC, HOST, VTS, PAINE, VLSID, GLSVLSI, ISVLSI, and Blockchain. He is the Program Co-Chair of PAINE, Vice-Co Program Chair of HOST, and Student Activities Chair of VTS. He is a senior member of IEEE and a member of ACM.