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WHiTe Compact Models
2021-11-03 04:40:20 | Compact Models | Contributor(s): Neal Graham Wood | doi:10.21981/6ERA-9P83
This package provides a set of 4H SiC (silicon carbide) high-temperature integrated device compact models, written in industry standard Verilog-A; currently included are a resistor and a JFET (junction field-effect transistor).
Peking University Analog-Switching Resistive Random Access Memory (RRAM) Verilog-A model
2021-02-02 02:43:58 | Compact Models | Contributor(s): Lixia Han, Linlin Cai, Jinfeng Kang, Xiaoyan Liu, Peng Huang | doi:10.21981/MRFT-C373
The Peking University Analog-switching RRAM physical model can capture the pulse conductance updates of analog RRAM devices rapidly and accurately. The model is described by Verilog-A and can be embedded in SPICE and Cadence for circuit simulations.
Unimore Resistive Random Access Memory (RRAM) Verilog-A Model
2019-06-08 22:48:08 | Compact Models | Contributor(s): Francesco Maria Puglisi, Tommaso Zanotti, Paolo Pavan | doi:10.21981/15GF-KX29
The Unimore RRAM Verilog-A model is a physics-based compact model of bipolar RRAM which includes cycle-to-cycle variability, thermal effects, self-heating, and multilevel Random Telegraph Noise (RTN).
MIT TFET compact model including the impacts of non-idealities
2017-05-08 02:34:24 | Compact Models | Contributor(s): Redwan Noor Sajjad, Ujwal Radhakrishna, Dimitri Antoniadis | doi:10.4231/D3XW47X6W
We present a compact model for tunnel FET that for the first time fits experimental transfer and output characteristics including the impact of non-idealities such as trap assisted tunneling and intrinsic band steepness.
Flexible Transition Metal Dichalcogenide Field-Effect Transistor (TMDFET) Model
2016-05-04 03:37:43 | Compact Models | Contributor(s): Morteza Gholipour, Deming Chen | doi:10.4231/D3TM72243
Verilog-A model of flexible transition metal dichalcogenide field-effect transistors (TMDFETs), considering effects when scaling the transistor size down to the 16-nm technology node.
Physics-Based Compact Model for Dual-Gate Bilayer Graphene FETs
2016-04-07 19:19:34 | Compact Models | Contributor(s): Jorge-Daniel Aguirre Morales, Sébastien Frégonèse, Chhandak Mukherjee, Cristell Maneux, Thomas Zimmer | doi:10.4231/D30C4SM1H
A compact model for simulation of Dual-Gate Bilayer Graphene FETs based on physical equations.
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