Tunnel FET Compact Model

By Hesameddin Ilatikhameneh1, Tarek Ahmed Ameen (editor)1, Fan Chen (editor)1, Ramon Salazar1, Gerhard Klimeck1, Joerg Appenzeller1, Rajib Rahman1

1. Purdue University

Model Tunnel FETs based on analytic modeling and WKB method

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Version 1.0 - published on 24 Aug 2016

doi:10.4231/D36D5PC3P cite this

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Usage

World usage

Location of all "Tunnel FET Compact Model" Users Since Its Posting

Simulation Users

111

5 12 19 31 35 42 43 49 61 63 68 72 76 77 81 81 85 90 93 97 106 107 108 110 111 111

Users By Organization Type
Type Users
Unidentified 78 (70.27%)
Educational - University 32 (28.83%)
Industry 1 (0.9%)
Users by Country of Residence
Country Users
us UNITED STATES 9 (33.33%)
in INDIA 8 (29.63%)
ve VENEZUELA, BOLIVARIAN REPUBLIC OF 3 (11.11%)
ru RUSSIAN FEDERATION 1 (3.7%)
es SPAIN 1 (3.7%)
it ITALY 1 (3.7%)
cn CHINA 1 (3.7%)
ro ROMANIA 1 (3.7%)
eg EGYPT 1 (3.7%)
tr TURKEY 1 (3.7%)

Simulation Runs

1,040

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Overview
Average Total
Wall Clock Time 1.92 hours 49.86 days
CPU time 32.86 seconds 5.7 hours
Interaction Time 46.55 minutes 20.17 days