Tunnel FET Compact Model

By Hesameddin Ilatikhameneh1, Tarek Ahmed Ameen (editor)1, Fan Chen (editor)1, Ramon Salazar1, Gerhard Klimeck1, Joerg Appenzeller1, Rajib Rahman1

1. Purdue University

Model Tunnel FETs based on analytic modeling and WKB method

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Version 1.0 - published on 24 Aug 2016

doi:10.4231/D36D5PC3P cite this

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Usage

World usage

Location of all "Tunnel FET Compact Model" Users Since Its Posting

Simulation Users

78

5 12 19 31 35 42 43 49 61 63 68 72 76 77 78

Users By Organization Type
Type Users
Unidentified 54 (69.23%)
Educational - University 23 (29.49%)
Industry 1 (1.28%)
Users by Country of Residence
Country Users
in INDIA 8 (34.78%)
us UNITED STATES 7 (30.43%)
ve VENEZUELA, BOLIVARIAN REPUBLIC OF 3 (13.04%)
bd BANGLADESH 1 (4.35%)
es SPAIN 1 (4.35%)
de GERMANY 1 (4.35%)
ie IRELAND 1 (4.35%)
pk PAKISTAN 1 (4.35%)

Simulation Runs

809

13 45 121 230 354 393 434 522 636 653 698 717 745 781 809
Overview
Average Total
Wall Clock Time 1.38 hours 30.2 days
CPU time 28.56 seconds 4.16 hours
Interaction Time 33.05 minutes 12.03 days