Tunnel FET Compact Model

By Hesameddin Ilatikhameneh1, Tarek Ahmed Ameen (editor)1, Fan Chen (editor)1, Ramon Salazar1, Gerhard Klimeck1, Joerg Appenzeller1, Rajib Rahman1

1. Purdue University

Model Tunnel FETs based on analytic modeling and WKB method

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Version 1.0 - published on 24 Aug 2016

doi:10.4231/D36D5PC3P cite this

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Usage

World usage

Location of all "Tunnel FET Compact Model" Users Since Its Posting

Cumulative Simulation Users

252

5 12 19 31 35 42 43 49 61 63 68 72 76 77 81 81 85 90 93 97 106 107 108 110 111 111 112 114 114 120 123 126 130 134 135 138 140 144 146 152 159 164 172 176 178 190 197 200 203 217 225 230 240 240 242 246 252 252 252

Users By Organization Type
Type Users
Unidentified 206 (81.75%)
Educational - University 44 (17.46%)
Industry 2 (0.79%)
Users by Country of Residence
Country Users
us UNITED STATES 13 (35.14%)
in INDIA 12 (32.43%)
ve VENEZUELA, BOLIVARIAN REPUBLIC OF 3 (8.11%)
cn CHINA 3 (8.11%)
ru RUSSIAN FEDERATION 1 (2.7%)
es SPAIN 1 (2.7%)
tr TURKEY 1 (2.7%)
au AUSTRALIA 1 (2.7%)
it ITALY 1 (2.7%)
ro ROMANIA 1 (2.7%)

Simulation Runs

2,705

10 36 91 168 248 283 317 390 480 494 531 547 566 588 616 675 700 768 790 806 901 919 997 1028 1038 1040 1045 1058 1066 1097 1111 1117 1175 1215 1223 1228 1230 1241 1244 1258 1267 1349 1405 1550 1572 1755 1902 1911 1926 1955 2025 2314 2679 2679 2687 2694 2704 2705 2705
Overview
Average Total
Wall Clock Time 1.15 hours 156.61 days
CPU time 13.16 seconds 11.93 hours
Interaction Time 19.18 minutes 43.48 days