Tunnel FET Compact Model

By Hesameddin Ilatikhameneh1, Tarek Ahmed Ameen (editor)1, Fan Chen (editor)1, Ramon Salazar1, Gerhard Klimeck1, Joerg Appenzeller1, Rajib Rahman1

1. Purdue University

Model Tunnel FETs based on analytic modeling and WKB method

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Version 1.0 - published on 24 Aug 2016

doi:10.4231/D36D5PC3P cite this

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Usage

World usage

Location of all "Tunnel FET Compact Model" Users Since Its Posting

Simulation Users

135

5 12 19 31 35 42 43 49 61 63 68 72 76 77 81 81 85 90 93 97 106 107 108 110 111 111 112 114 114 120 123 126 130 134 135 135

Users By Organization Type
Type Users
Unidentified 98 (72.59%)
Educational - University 36 (26.67%)
Industry 1 (0.74%)
Users by Country of Residence
Country Users
us UNITED STATES 11 (35.48%)
in INDIA 9 (29.03%)
ve VENEZUELA, BOLIVARIAN REPUBLIC OF 3 (9.68%)
cn CHINA 2 (6.45%)
bd BANGLADESH 1 (3.23%)
pk PAKISTAN 1 (3.23%)
de GERMANY 1 (3.23%)
ru RUSSIAN FEDERATION 1 (3.23%)
es SPAIN 1 (3.23%)
it ITALY 1 (3.23%)

Simulation Runs

1,224

10 36 91 168 248 283 317 390 480 494 531 547 566 588 616 675 700 768 790 806 901 919 997 1028 1038 1040 1045 1058 1066 1097 1111 1117 1175 1215 1223 1224
Overview
Average Total
Wall Clock Time 1.56 hours 52.05 days
CPU time 29.31 seconds 6.52 hours
Interaction Time 38.17 minutes 21.23 days