This seminar is part of the MEST webinar archive that can be found at the online course MEST Webinar Seminar Series. Enrollment is free and unrestricted. Once enrolled you will be able to view all past webinars.

To gain a better understanding of the learning experience, we strongly ask that you complete the associated pre-learning experience and post-learning experience surveys for this seminar:
• Please complete this 3-question survey before viewing the lecture
• Please complete this short survey after viewing the lecture

This webinar will provide an overview of the most common asynchronous design techniques and their Power, Performance, Area, and Security (PPAS) tradeoffs with a focus on information leakage. This webinar will conclude with recommendations on when certain asynchronous approaches may be appropriate and provide superior PPAS to traditional synchronous design.

To see the schedule for upcoming live webinars please visit the MEST Webinar Calendar.

William Koven is a Galois research engineer. Previously he was co-founder and CEO of Reduced Energy Microsystems (REM), a company focused on low power, high-performance edge computing. He received his B.S. in engineering from Harvey Mudd College, where he was a Clay-Wolkin Fellow. Prior to co-founding REM, William worked at AMD and at Intel in both product groups and Intel Labs. He has been involved in many production chip tapeouts as well as research chip development. He has also developed several novel asynchronous circuit architectures and continues to be heavily involved in the asynchronous design community.

National Microelectronics Security Training Center (MEST).

Researchers should cite this work as follows:

• William Koven (2024), "Asynchronous Design: Responsible Use," https://nanohub.org/resources/39001.

  BibTex | EndNote

1. Hardware Security
2. MEST
3. microelectronics
4. security