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Abstract
Open-source Chip design using OpenLane and OpenROAD
Welcome to the st4stars2023 Simulation Tool (sim2l) powered by OpenLane! This tool allows you to simulate and verify the design of integrated circuits (ICs) efficiently using the OpenLane framework. OpenLane is a robust and open-source ASIC (Application-Specific Integrated Circuit) synthesis flow that supports a variety of physical design automation (PDA) tasks, from RTL (Register Transfer Level) to GDSII (Graphic Data System II) layout. Current templae is based on the outlet-8227 work done for the Stars Program 2023 @ Purdue.
Key Features
- Seamless Integration with OpenLane: Utilize the comprehensive suite of tools provided by OpenLane to perform synthesis, placement, routing, and optimization of your chip designs.
- Interactive Jupyter Notebooks: Get hands-on with chip simulation through interactive Jupyter Notebooks, which guide you step-by-step through the design and simulation process.
Getting Started
To get started with chip simulation using OpenLane, select one of the Jupyter Notebook versions:
- Beginner Version - Web Application, Under construction .
- Intermediate Version - For users who are familiar with the basics and want to explore more advanced features and customization options within OpenLane.
- Advanced Version - raw version that allow users to interact with the sim2l
How to Use the Tool
- Select a Version
- Run Simulations: Execute the cells in the notebook to run simulations (or click on the simulate button), observe results, and modify parameters to see their effects on the chip design.
Additional Resources
- OpenLane Documentation - Learn more about the OpenLane framework and its capabilities.
We hope you find this tool useful for your chip simulation needs. Happy designing!
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