Description

In 1973, SPICE was introduced to the world by Professor Donald O. Pederson of the University of California at Berkeley, and a new era of computer-aided design (CAD) tools was born. As its name implies, SPICE is a "Simulation Program with Integrated Circuit Emphasis." You give it a description of an electrical circuit, made up of resistors, capacitors, inductors, and power sources, and SPICE will predict the performance of that circuit. Instead of bread-boarding new designs in the lab, circuit designers found they could optimize their designs on computers–in effect, using computers to build better computers. Since its introduction, SPICE has been commercialized and released in a dozen variants, such as H-SPICE, P-SPICE, and ADVICE.

Learn more about circuit simulation from the resources on this site, listed below. You might even acquire a taste for SPICE by running examples online.

Downloads (1-6 of 6)

1. A UCSD analytic TFET model

   18 Dec 2015 | | Contributor(s):: Jianzhi Wu, Yuan Taur

   A continuous, analytic I-V model is developed for double-gate and nanowire tunnel FETs with 3D density of states, including depletion in the source. At the core of the model is a gate-controlled channel potential that satisfies the source and drain boundary conditions. Verified by...

2. SPICE Model of Graphene Nanoribbon FETs (GNRFET)

   12 Jul 2013 | | Contributor(s):: Ying-Yu Chen, Morteza Gholipour, Artem Rogachev, Amit Sangai, Deming Chen

   This is a SPICE compatible model for both MOS- and Schottky-Barrier-type Graphene Nano-Ribbons Field-Effect Transistor. These MOS-GNRFET and SB-GNRFET models are implemented in HSPICE and can be used for circuit simulations. The model is implemented based on the...

3. NanoV: Nanowire-based VLSI Design

   08 Sep 2010 | | Contributor(s):: muzaffer simsir

   In the coming decade, CMOS technology is expected to approach its scaling limitations. Among the proposed nanotechnologies, nanowires have the edge in the size of circuits and logic arrays that have already been fabricated and experimentally evaluated. For this technology, logic-level design...

4. Reed-Muller Reversible Logic Synthesizer (RMRLS) 0.2

   out of 5 stars 

   04 Jan 2008 | | Contributor(s):: James Donald, Pallav Gupta

   Reed-Muller Reversible Logic Synthesis tool (a.k.a. RELOS) is a tool for the synthesis of reversible functions based on positive-polarity Reed-Muller expressions. The second release of RMRLS features reversible logic synthesis with SWAP, Fredkin, and Peres gates. This work was done under the...

5. ThrEshold Logic Synthesizer (TELS) and Majority Logic Synthezier (MALS)

   out of 5 stars 

   09 Oct 2007 | | Contributor(s):: Pallav Gupta

   TELS and MALS are threshold and majority/minority logic synthesis tools that were developed by Rui Zhang and Pallav Gupta under the supervision of Prof. Niraj K. Jha of Princeton University. Dr. Lin Zhong, of Rice University, was also a contributor.Both of these tools have been integrated into...

6. NanoMOS 2.5 Source Code Download

   out of 5 stars 

   22 Feb 2005 | | Contributor(s):: Zhibin Ren, Sebastien Goasguen

   NanoMOS is a 2-D simulator for thin body (less than 5 nm), fully depleted, double-gated n-MOSFETs. A choice of five transport models is available (drift-diffusion, classical ballistic, energy transport, quantum ballistic, and quantum diffusive). The transport models treat quantum effects in the...