Tags: FinFET

All Categories (1-16 of 16)

  1. Achintya Priydarshi

    https://nanohub.org/members/145038

  2. how to decide device characteristic while designing a device?

    Closed | Responses: 0

    Hello,

    https://nanohub.org/answers/question/1652

  3. Finfet raw files needed

    Closed | Responses: 0

     

    Hello, I wanted to simulate these files using HSpice. I wanted to see the transfer characteristics for temperature variation. Unfortunately the look up table is designed in...

    https://nanohub.org/answers/question/1566

  4. HIMANSHU SAINI

    https://nanohub.org/members/111503

  5. 7nm Si FinFET Models with Symmetric and Asymmetric Underlap for Circuit Simulations

    23 Aug 2013 | Downloads | Contributor(s): Arun Goud Akkala, Sumeet Kumar Gupta, Sri Harsha Choday, Kaushik Roy

    This tarball contains Verilog-A compact lookup table models for 7nm channel length Si FinFET with different underlaps which can be used in HSPICE netlists for circuit simulations....

    https://nanohub.org/resources/19195

  6. Pankaj Kumar Pal

    https://nanohub.org/members/82565

  7. Mohamed Tarek Ghoneim

    Keywords: device physics, flexible electronics, nanotechnology, graphene, nonvolatile memory, reliability, CMOS, physical and electrical characterization, emerging devices, power management, VLSI,...

    https://nanohub.org/members/77955

  8. How to get the Finfet model library file for cadence for simulation ???

    Closed | Responses: 0

    https://nanohub.org/answers/question/1148

  9. How to get a model file for FinFET  ???

    Closed | Responses: 0

    https://nanohub.org/answers/question/1146

  10. Asrulnizam Abd Manaf

    Dr. Asrulnizam bin Abd Manaf received the BEng in Electrical and Electronic Engineering from Toyohashi University of Technology, Japan in 2001. Then, he worked as electrical engineer at...

    https://nanohub.org/members/70293

  11. Are there any clear advantages to either UTB SOI vs FinFet devices?

    Open | Responses: 1

    I have been doing some reading on these devices and it seems that both structures give the gate more control and suppress the influence of the drain voltage on the channel. So, is there a clear...

    https://nanohub.org/answers/question/934

  12. keerti kumar korlapati

    https://nanohub.org/members/55518

  13. Vivek Asthana

    https://nanohub.org/members/49925

  14. Quantum and Thermal Effects in Nanoscale Devices

    18 Sep 2008 | Online Presentations | Contributor(s): Dragica Vasileska

    To investigate lattice heating within a Monte Carlo device simulation framework, we simultaneously solve the Boltzmann transport equation for the electrons, the 2D Poisson equation to get the...

    https://nanohub.org/resources/5448

  15. MuGFET

    01 May 2008 | Tools | Contributor(s): SungGeun Kim, Gerhard Klimeck, Sriraman Damodaran, Benjamin P Haley

    Simulate the nanoscale multigate-FET structures (finFET and nanowire) using drift diffusion approaches

    https://nanohub.org/resources/NANOFINFET

  16. MuGFET: First-Time User Guide

    28 Apr 2008 | Teaching Materials | Contributor(s): SungGeun Kim, Sriraman Damodaran, Benjamin P Haley, Gerhard Klimeck

    MuGFET is a simulation tool for nano-scale multi-gate FET structures. This document provides instructions on how to use MuGFET. MuGFET users can use also the PROPHET or the PADRE tool. Either...

    https://nanohub.org/resources/4470