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A Performance Comparison of Algebraic Multigrid Preconditioners on GPUs and MIC
Online Presentations | 04 Feb 2016 | Contributor(s):: Karl Rupp
Algebraic multigrid (AMG) preconditioners for accelerators such as graphics processing units (GPUs) and Intel's many-integrated core (MIC) architecture typically require a careful, problem-dependent trade-off between efficient hardware use, robustness, and convergence rate in order to...
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Advanced Parallel CPU Programming Part 1: OmpSs Quick Overview
Online Presentations | 29 Aug 2013 | Contributor(s):: NanoBio Node, Xavier Teruel
High Performance Computing --> Some basic concepts, Supercomputers nowadays, Parallel programming models OmpSs Introduction --> OmpSs main features, A Practical Example: Cholesky factorization BSC’s Implementation --> Mercurium Compiler, Nanos++ Runtime Library, Visualization Tools
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Challenges and Strategies for High End Computing
Online Presentations | 20 Dec 2007 | Contributor(s):: Katherine A. Yelick
This presentation was one of 13 presentations in the one-day forum, "Excellence in Computer Simulation," which brought together a broad set of experts to reflect on the future of computational science and engineering.
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Charles Taylor Patrick Gillespie
Mr. Charles Taylor Patrick Gillespie is currently pursuing a LL.M. in Intellectual Property at Santa Clara University School of Law and focusing on Nanotechnology and the Law. He graduated from the...
https://nanohub.org/members/33082
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Development of a Nanoelectronic 3-D (NEMO 3-D ) Simulator for Multimillion Atom Simulations and Its Application to Alloyed Quantum Dots
Papers | 14 Jan 2008 | Contributor(s):: Gerhard Klimeck, Timothy Boykin
Material layers with a thickness of a few nanometers are common-place in today’s semiconductordevices. Before long, device fabrication methods will reach a point at which the other two devicedimensions are scaled down to few tens of nanometers. The total atom count in such deca-nanodevices is...
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Edoardo Emilio Coronado
https://nanohub.org/members/66233
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High Performance Computing Training Workshop
Workshops | 09 Oct 2007
The Computing Research Institute and the Rosen Center for Advanced Computing hosted a training workshop on High Performance Computing August 6 &7, and September 10 & 11, 2007. The goal of this workshop is to increase the attendees’ knowledge of parallel architectures and parallel programming on...
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HPCW High-end HPC Architectures
Online Presentations | 09 Oct 2007 | Contributor(s):: Mithuna Thottethodi
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HPCW Introduction to Parallel Programming with MPI
Online Presentations | 05 Dec 2007 | Contributor(s):: David Seaman
Single-session courseillustrating message-passing techniques. The examples include point-to-pointand collective communication using blocking and nonblocking transmission. Oneapplication illustrates the manager/worker model with buffered communications.Code examples provided in C, C++, Fortran 77,...
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HPCW Parallel Programming Models
Online Presentations | 09 Oct 2007 | Contributor(s):: Sam Midkiff
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Illinois ECE 498AL: Programming Massively Parallel Processors
Courses | 11 Aug 2009 | Contributor(s):: Wen-Mei W Hwu
Spring 2009 Virtually all semiconductor market domains, including PCs, game consoles, mobile handsets, servers, supercomputers, and networks, are converging to concurrent platforms. There are two important reasons for this trend. First, these concurrent processors can potentially offer more...
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Illinois ECE 498AL: Programming Massively Parallel Processors, Lecture 10: Control Flow
Online Presentations | 01 Sep 2009 | Contributor(s):: Wen-Mei W Hwu
Control FlowTopics: Terminology Review How Thread Blocks are Partitioned Control Flow Instructions Parallel Reduction A Vector Reduction Example A simple Implementation Vector Reduction With Bank Conflicts Vector Reduction With Branch Divergence Predicted Execution Concept Instruction Prediction...
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Illinois ECE 498AL: Programming Massively Parallel Processors, Lecture 6: CUDA Memories - Part 2
Online Presentations | 20 Aug 2009 | Contributor(s):: Wen-Mei W Hwu
CUDA Memories Part2Topics: Tiled Multiply Breaking Md and Nd into Tiles Tiled Matrix Multiplication Kernel CUDA Code - Kernel Execution Configuration First Order Size considerations in G80 G80 Shared Memory and Threading Tiling Size Effects Typical Structure of a CUDA ProgramThese lecture were...
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Illinois ECE 498AL: Programming Massively Parallel Processors, Lecture 9: Memory Hardware in G80
Online Presentations | 30 Aug 2009 | Contributor(s):: Wen-Mei W Hwu
Memory Hardware in G80Topics: CUDA Device Memory Space Parallel Memory Sharing SM Memory Architecture SM Register File Programmer view of Register File Matrix Multiplication Example More on Dynamic Partitioning ILP vs. TLP Memory Layout of a Matrix in C Constants Shared Memory Parallel Memory...
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Intel Advisor XE 2013
Presentation Materials | 12 Mar 2013 | Contributor(s):: Intel
This is a presentation Intel engineer James Tullos presented at Purdue University on March 8, 2013.
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Intel Inspector XE 2013 An Introduction
Presentation Materials | 12 Mar 2013 | Contributor(s):: Holly Wilper
This is a presentation Intel engineer Holly Wilper presented at Purdue University on March 8, 2013.
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Intel VTune Amplifier XE 2013: An introduction
Presentation Materials | 12 Mar 2013 | Contributor(s):: Intel
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Intel Xeon Phi Programming
Presentation Materials | 12 Mar 2013 | Contributor(s):: James Tullos
This is a presentation Intel engineer James Tullos presented at Purdue University on March 8, 2013.
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Introduction to Parallel Programming with MPI
Online Presentations | 24 Nov 2008 | Contributor(s):: David Seaman
Single-session course illustrating message-passing techniques. The examples include point-to-point and collective communication using blocking and nonblocking transmission. One application illustrates the manager/worker model with buffered communications. Code examples provided in C, C++, Fortran...
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Introduction to TotalView
Online Presentations | 24 Nov 2008 | Contributor(s):: David Seaman
This single-session course presents an introduction to the use of the TotalView parallel debugger available on Purdue's Linux systems.