Fixed source-to-channel junction?

Is the source-to-channel junction always a fixed 1e-20? Wouldn't it be better to have a parameter (with a default of 1e-20)?

x_jun_s = 1e-20; // x-position defining the source-to-channel junction

Is the 1e-20 in this equation always 1e-20, or is it actually equal to x_jun_s?

x_jun_d = lch_lim - 1e-20; // x-position defining the drain-to-channel junction

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Alexander Kloes@ onIn its current version, the potential model does not take into account any gate underlap or overlap. Therefore, x_jun_s = 0.

During model development, the parameter x_jun_s was experimental; in the initial model it was not a fixed parameter.

Now, it could simply be set to zero, but in order to prevent any numerical issues (which in case of such a complex analytical potential model is not easy to see...) the value 1e-20 was chosen.

As you see: the model itself has undergone many, many iterations even for the original code in Matlab (the potential model is still under further development...). That is the reason why the Verilog code is somehow in a early stage, too.

However, we really appreciate your inputs for improvement!

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