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This is a collection of NEEDS resources on compact models aimed at first-time compact model developers. Readers can obtain a good understanding of compact model development in general by going through this training. Later on, readers are encouraged to dive into components of this collection for in-depth study.
In this section, we assume the reader has no background in circuit simulation but with limited knowledge in physics. Gives a broad introduction to the role of compact model in circuit simulation.
explains the motivation behind compact models with a bit of history
show the difference between PDE based CAD and compact models in circuit simulations, including advantage and disadvantage of each.
importance of compact model in today’s IC development. What are the current status and commonly used model?. What are the main issues?
software related to compact model development including various SPICE
How one abstracts a circuit from layout into gridded nodes with connected components using Netlist format.
How the modified nodal analysis is used to term the netlist into a system of matrix equations
Illustrate the idea of numerical iteration using Newton-Ralphson to seek the solution of the system of equations.
Use a RLC circuit as an example to show working under MAPP environment
Starting with a simple RLC circuit, we illustrate step-by-step how to prototype this compact model in MAPP.
Same RLC circuit as previous section, we write it in Verilog-A. Explain the differences between Verilog-A and MAPP approaches.
Show how to compile the Verilog-A code into C and connect with Spectre SPICE simulator. Examine the C library to understand how Verilog-A code is turned into basic MNA equations.
Showcase VAPP using the RLC circuit Verilog-A. b. Evaluate the model and spot the issues
Use the first version of MVS model as example.
Showcase VALint and discuss bad practices in Verilog-A