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Nano-Engineered Electronic Device Simulation Node

NEEDS has a vision for a new era of electronics that couples the power of billion-transistor CMOS technology with the new capabilities of emerging nano-devices and a charter to create high-quality models and a complete development environment that enables a community of compact model developers.

NEEDS Team: Purdue, MIT, U.C. Berkeley, and Stanford.

NEEDS 2017 Annual Review (May 8-9) has concluded. Posters now available online. 
(03/27/2017) Paper "Well-Posed Device Models for Electrical Circuit Simulation" by A. Gokcen Mahmutoglu, Tianshi Wang, Archit Gupta, and Jaijeet Roychowdhury
(03/09/2017) NEEDS announces the new public release of MAPP, a MATLAB-based platform for prototyping numerical models and simulation algorithms, and VAPP, a MATLAB tool that translates Verilog-A device models into ModSpec.  
(03/07/2017) NEWEST COMPACT MODEL RELEASE:  MIT Virtual Source Negative Capacitance (MVSNC) Model and UARK SiC Power MOSFET Model See Compact Models Page

Compact Models

Verilog-A format
supporting resources


Compact models:

Tools for devlopers including MAPP & VALint.

 VALint now in open BETA

Compact models: resources                                                                                        

Seminars and tutorials for developing and publishing compact models

 Publish your compact model in NEEDS

nanoscience to systems

Physically-detailed simulations
system level tools

 Stanford script-based toolkit for system analysis

nanoscience: Seminars, Courses, etc.                                                                                                   

NEEDS Seminars, workshops, nanoHUB-U and more

 Seminar series on devices for 5 nm technology