1. The R3 Model: Homework Solutions

   Online Presentations | 07 Feb 2015 | Contributor(s): Colin McAndrew

2. The R3 Model: Verilog-A Code (A Look at the Code)

   Online Presentations | 02 Feb 2015 | Contributor(s): Colin McAndrew

   This talk presents a quick run-through look at the Verilog-A code for the R3 transistor model. 

3. The R3 Model: Homework

   Online Presentations | 02 Feb 2015 | Contributor(s): Colin McAndrew

4. How to Write, Develop and Implement a Real Compact Model

   Workshops | 31 Jan 2015 | Contributor(s): Colin McAndrew

   Compact models must get the physics right, work reliably over bias, geometry, and temperature, interact properly with the circuit simulators in which they are implemented, run efficiently, and follow impeccable software development practices. This workshop will be a detailed deep-dive into an...

5. The R3 Model: Verilog-A Code

   Online Presentations | 28 Jan 2015 | Contributor(s): Colin McAndrew

   This talk presents an in depth look at the Verilog-A code for the R3 transistor model.  It also includes some general guidelines for writing compact models.

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1. 

   PSPHV LDMOS

   19 Nov 2021 | Contributor(s): Colin McAndrew, kejun xia | doi:10.21981/93B1-9539

   This is an update to version 1.0.6 of the PSPHV LDMOS model (an enhanced PSP103.6 model for the core MOS transistor, an updated JFETIDG model for the drift region, JUNCAP2 for the pn-junction diodes, PSP MOS for gate-drain overlap capacitance.

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   PSPHV LDMOS

   16 Aug 2020 | Contributor(s): Colin McAndrew, kejun xia | doi:10.21981/H8TZ-RM88

   PSPHV consists of an enhanced PSP103.6 model for the core MOS transistor, an updated JFETIDG model for the drift region, JUNCAP2 for the pn-junction diodes, and two 3-terminal MOS capacitors based on PSP for the gate-drain overlap capacitance.

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   PSPHV LDMOS

   17 Apr 2020 | Contributor(s): Colin McAndrew | doi:10.21981/NK3R-W064

   PSPHV consists of an enhanced PSP103.6 model for the core MOS transistor, an updated JFETIDG model for the drift region, JUNCAP2 for the pn-junction diodes, and two 3-terminal MOS capacitors based on PSP for the gate-drain overlap capacitance.

4. 

   JFETIDG Model for Independent Dual-Gate JFETs

   19 Jul 2017 | Contributor(s): Colin McAndrew, Kejun Xia | doi:10.4231/D3KK94F1N

   JFETIDG is a compact model for independent dual-gate JFETs. It is also applicable to: resistors with metal shields; the drift region of LDMOS transistors; the collector resistance of vertical bipolar transistors; and junctionless MOS transistors.

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   JFETIDG Model for Independent Dual-Gate JFETs

   24 Mar 2017 | Contributor(s): Colin McAndrew, Kejun Xia | doi:10.4231/D3TD9N91H

   JFETIDG is a compact model for independent dual-gate JFETs. It is also applicable to: resistors with metal shields; the drift region of LDMOS transistors; the collector resistance of vertical bipolar transistors; and junctionless MOS transistors.

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