Stanford University Resistive-Switching Random Access Memory (RRAM) Verilog-A Model 1.0.0
The Stanford University RRAM Model is a SPICE-compatible compact model which describes switching performance for bipolar metal oxide RRAM.
Listed in Compact Models | publication by group NEEDS: New Era Electronic Devices and Systems
Additional materials available
Version 1.0.0 - published on 23 Oct 2014 doi:10.4231/D37H1DN48 - cite this
Licensed under NEEDS Modified CMC License according to these terms
Citations Non-affiliated (4) | Affiliated (3)
Non-affiliated authors
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Basma Hajri, Mohammad Mansour, Ali Chehab, Hassen Aziza, (2020), "A Lightweight Reconfigurable RRAM-based PUF For Highly Secure Applications", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems \DFT), : pg: -, IEEE, (DOI: DOI: 10.1109/DFT50435.2020.9250829)
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Basma Hajri, Mohammad Mansour, Ali Chehab, Hassen Aziza, (2017), "Oxide-based RRAM Models For Circuit Designers: A Comparative Analysis", 2017 12th International Conference on Technology Design &of Integrated Systems In Nanoscale Era \DTIS), : pg: 1-6, (DOI: 10.1109/DTIS.2017.7930176)
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Lei Zhao, Lei Jiang, Youtao Zhang, Nong Xiao, Jun Yang, (2017), "Constructing Fast And Energy Efficient 1TnR Based ReRAM Crossbar Memory", 2017 18th International Symposium on Quality Electronic Design \ISQED), : pg: 1-7
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Gerardo Gonzalez-Cordero, Francisco Jimenez-Molinos, Juan Roldan, Mireia Gonzalez, Francesca Campabadal, (2017), "In-depth Study Of The Physics Behind Resistive Switching In TiN/Ti/HfO2/W Structures", J. Vac. Sci. Technol. B, 35, 1: pg: 01A110-1-01A110-5, (DOI: 10.1116/1.4973372)
Affiliated authors
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Zizhen Jiang, Yi Wu, S Yu, Lin Yang, Kay Song, Zia Karim, H.-S.P. Wong, (2016), "A Compact Model For Metal-Oxide Resistive Random Access Memory With Experiment Verification", IEEE Transactions on Electron Devices, 63, 5: pg: 1884-1892, (DOI: 10.1109/TED.2016.2545412)
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Sukru Erylmaz, Siddharth Joshi, Emre Neftci, Weier Wan, Gert Cauwenberghs, H.-S.P. Wong, (2016), "Neuromorphic Architectures With Electronic Synapses", Quality Electronic Design \ISQED), 2016 17th International Symposium on, : pg: 1-6, 1948-3295 (DOI: 10.1109/ISQED.2016.7479186)
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S. Eryilmaz, Duygu Kuzum, Shimeng Yu, H.-S.P. Wong, (2015), "Device And System Level Design Considerations For Analog-Non-Volatile-Memory Based Neuromorphic Architectures", Electron Devices Meeting \IEDM) 2015, IEEE International, : pg: 1-4
NEEDS: New Era Electronic Devices and Systems
This publication belongs to the NEEDS: New Era Electronic Devices and Systems group.