VALint: the NEEDS Verilog-A Checker (BETA)

By Xufeng Wang1, Geoffrey Coram2, Colin McAndrew3

1. Purdue University 2. Analog Devices, Inc. 3. Freescale Semiconductor

Verilog-A lint and pretty printer created by NEEDS

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Version 1.0.0 - published on 31 Mar 2017

doi:10.4231/D3HX15S0V cite this

Open source: license | download

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Usage

World usage

Location of all "VALint: the NEEDS Verilog-A Checker (BETA)" Users Since Its Posting

Cumulative Simulation Users

196

9 20 23 32 36 47 50 55 56 60 63 64 64 67 70 72 74 75 79 81 85 91 92 92 95 100 106 109 112 113 115 119 120 123 127 129 132 135 135 137 141 141 142 143 144 147 149 149 153 157 158 159 161 161 163 163 163 163 166 166 169 169 171 175 176 177 179 179 179 180 181 182 184 184 184 184 185 185 188 188 189 189 192 193 194 195 195 195 196

Users By Organization Type
Type Users
Unidentified 149 (76.02%)
Educational - University 39 (19.9%)
Industry 7 (3.57%)
National Lab 1 (0.51%)
Users by Country of Residence
Country Users
us UNITED STATES 22 (57.89%)
in INDIA 5 (13.16%)
de GERMANY 3 (7.89%)
jp JAPAN 2 (5.26%)
pl POLAND 1 (2.63%)
br BRAZIL 1 (2.63%)
tn TUNISIA 1 (2.63%)
fr FRANCE 1 (2.63%)
ve VENEZUELA, BOLIVARIAN REPUBLIC OF 1 (2.63%)
kr KOREA, REPUBLIC OF 1 (2.63%)

Simulation Runs

1,100

44 146 174 286 312 366 376 404 430 460 470 480 480 486 498 506 510 527 553 567 591 625 633 635 655 671 685 697 713 717 723 743 745 751 773 781 787 797 809 825 843 843 845 849 859 869 877 877 893 907 909 916 919 919 939 939 939 939 949 949 961 961 983 1009 1014 1020 1032 1032 1032 1034 1042 1044 1050 1050 1052 1054 1056 1056 1064 1064 1066 1066 1084 1090 1092 1096 1096 1096 1100
Overview
Average Total
Wall Clock Time 4.71 hours 108.23 days
CPU time 57.51 seconds 8.8 hours
Interaction Time 2.63 hours 60.38 days