VALint: the NEEDS Verilog-A Checker (BETA)

By Xufeng Wang1, Geoffrey Coram2, Colin McAndrew3

1. Purdue University 2. Analog Devices, Inc. 3. Freescale Semiconductor

Verilog-A lint and pretty printer created by NEEDS

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Version 1.0.0 - published on 31 Mar 2017

doi:10.4231/D3HX15S0V cite this

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Usage

World usage

Location of all "VALint: the NEEDS Verilog-A Checker (BETA)" Users Since Its Posting

Simulation Users

126

9 20 23 32 36 47 50 55 56 60 63 64 64 67 70 72 74 75 79 81 85 91 92 92 95 100 106 109 112 113 115 119 120 123 126

Users By Organization Type
Type Users
Unidentified 84 (66.67%)
Educational - University 35 (27.78%)
Industry 6 (4.76%)
National Lab 1 (0.79%)
Users by Country of Residence
Country Users
us UNITED STATES 21 (60%)
in INDIA 4 (11.43%)
de GERMANY 3 (8.57%)
ru RUSSIAN FEDERATION 1 (2.86%)
br BRAZIL 1 (2.86%)
fr FRANCE 1 (2.86%)
kr KOREA, REPUBLIC OF 1 (2.86%)
bd BANGLADESH 1 (2.86%)
tn TUNISIA 1 (2.86%)
ve VENEZUELA, BOLIVARIAN REPUBLIC OF 1 (2.86%)

Simulation Runs

769

44 146 174 286 312 366 376 404 430 460 470 480 480 486 498 506 510 527 553 567 591 625 633 635 655 671 685 697 713 717 723 743 745 751 769
Overview
Average Total
Wall Clock Time 3.51 hours 56.17 days
CPU time 1.01 minutes 6.48 hours
Interaction Time 2.49 hours 39.89 days