VALint: the NEEDS Verilog-A Checker (BETA)

By Xufeng Wang1, Geoffrey Coram2, Colin McAndrew3

1. Purdue University 2. Analog Devices, Inc. 3. Freescale Semiconductor

Verilog-A lint and pretty printer created by NEEDS

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Version 1.0.0 - published on 31 Mar 2017

doi:10.4231/D3HX15S0V cite this

Open source: license | download

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Usage

World usage

Location of all "VALint: the NEEDS Verilog-A Checker (BETA)" Users Since Its Posting

Cumulative Simulation Users

163

9 20 23 32 36 47 50 55 56 60 63 64 64 67 70 72 74 75 79 81 85 91 92 92 95 100 106 109 112 113 115 119 120 123 127 129 132 135 135 137 141 141 142 143 144 147 149 149 153 157 158 159 161 161 163 163 163 163 163

Users By Organization Type
Type Users
Unidentified 118 (72.39%)
Educational - University 37 (22.7%)
Industry 7 (4.29%)
National Lab 1 (0.61%)
Users by Country of Residence
Country Users
us UNITED STATES 21 (56.76%)
in INDIA 5 (13.51%)
de GERMANY 3 (8.11%)
jp JAPAN 2 (5.41%)
bd BANGLADESH 1 (2.7%)
ru RUSSIAN FEDERATION 1 (2.7%)
gb UNITED KINGDOM 1 (2.7%)
pl POLAND 1 (2.7%)
br BRAZIL 1 (2.7%)
tn TUNISIA 1 (2.7%)

Simulation Runs

939

44 146 174 286 312 366 376 404 430 460 470 480 480 486 498 506 510 527 553 567 591 625 633 635 655 671 685 697 713 717 723 743 745 751 773 781 787 797 809 825 843 843 845 849 859 869 877 877 893 907 909 916 919 919 939 939 939 939 939
Overview
Average Total
Wall Clock Time 5.34 hours 104.78 days
CPU time 59.82 seconds 7.83 hours
Interaction Time 2.94 hours 57.73 days