
Stephen Remillard
https://nanohub.org/members/202557

ABACUS—Introduction to Semiconductor Devices
When we hear the term semiconductor device, we may think first of the transistors in PCs or video game consoles, but transistors are the basic component in all of the electronic devices we use in...
https://nanohub.org/wiki/EduSemiconductor

Semiconductor & graphene mixtures, printable, for FETs, VFETS?
Closed  Responses: 2
We tried synthesizing diketopyrroles, and we could not make them.
We have fiddled with P3HT, and we are concerned about its long term compatibility with our ionic liquid...
https://nanohub.org/answers/question/2036

nMOSFET RF and noise model on standard 45nm SOI technology
01 Jan 2017  Compact Models  Contributor(s):
By Yanfei Shen^{1}, Saeed Mohammadi^{1}
Purdue University
A compact scalable model suitable for predicting high frequency noise and nonlinear behavior of Ntype Metal Oxide Semiconductor (NMOS) transistors is presented.
https://nanohub.org/publications/160/?v=1

MATLAB: Negative Capacitance (NC) FET Model
05 Dec 2015   Contributor(s):: Muhammad Abdul Wahab, Muhammad A. Alam
MATLAB model that calculates the QV, CV, and IV characteristics of the conventional MOSFET and NCFET.

A Tutorial Introduction to NegativeCapacitor Landau Transistors: Perspectives on the Road Ahead
04 Dec 2015   Contributor(s):: Muhammad A. Alam
In this talk, I use a simple graphical approach to demystify the device and explain why the experimental results are easy to misinterpret. Since the NCFET is just a special case of a much broader class of phasechange devices and systems (e.g., transistors, memories, MEMS, logicinmemory...

Green Light on Germanium
02 Nov 2015   Contributor(s):: peide ye
This talk will review recent progress as well as challenges on Ge research for future logic applications with emphasis on the breakthrough work at Purdue University on Ge nFET which leads to the demonstration of the world first Ge CMOS circuits on Si substrates. Ge device technology includes...

how to simulate insulator in a GNRFET with matlab?
Closed  Responses: 0
I want to apply gate voltage on a graphene nanoribbon as a channel in a GNRFET. then I want to solve poisson equation but I need to know the voltage on channel as the boundary...
https://nanohub.org/answers/question/1583

Ivan C R nascimento
https://nanohub.org/members/121504

Himanshu Rai
https://nanohub.org/members/117669

Convergence problem, take smaller steps
Closed  Responses: 1
I receive this error when running the MOSFET tool. Any one can suggest a solution
https://nanohub.org/answers/question/1488

Models for SETs in PSpice
Closed  Responses: 0
Hello. I am trying to simulate hybrid circuits (cMOS SET transistors) and I can't find models for SET, anywhere... I only want a SET that can simulate properly along with regular...
https://nanohub.org/answers/question/1399

MOSFET Simulation
04 Oct 2013   Contributor(s):: Chen Shang, Sankarsh Ramadas, Tanya Faltens, derrick kearney, Krishna Madhavan
Displays drain current as a function of sourcedrain voltage for different values of gate voltage, gate dimensions, substrate material, and oxide material in an ntype MOSFET.

Al Key
Technology refresh
https://nanohub.org/members/89988

Tunnel FETs  Device Physics and Realizations
27 Jun 2013   Contributor(s):: Joachim Knoch
Here, the operating principles of TFETs will be discussed in detail and experimental realizations as well as simulation results will be presented. In particular, the role of the injecting source contact will be elaborated on.

Device Physics Studies of IIIV and Silicon MOSFETS for Digital Logic
25 Jun 2013   Contributor(s):: Himadri Pal
IIIV's are currently gaining a lot of attraction as possible MOSFET channel materials due to their high intrinsic mobility. Several challenges, however, need to be overcome before IIIV's can replace silicon (Si) in extremely scaled devices. The effect of low densityofstates of IIIV...

IIIV Nanoscale MOSFETS: Physics, Modeling, and Design
25 Jun 2013   Contributor(s):: Yang Liu
As predicted by the International Roadmap for Semiconductors (ITRS), power consumption has been the bottleneck for future silicon CMOS technology scaling. To circumvent this limit, researchers are investigating alternative structures and materials, among which IIIV compound semiconductorbased...

Computational and Experimental Study of Transport in Advanced Silicon Devices
27 Jun 2013   Contributor(s):: Farzin Assad
In this thesis, we study electron transport in advanced silicon devices by focusing on the two most important classes of devices: the bipolar junction transistor (BJT) and the MOSFET. In regards to the BJT, we will compare and assess the solutions of a physically detailed microscopic model to...

Exploring New Channel Materials for Nanoscale CMOS
27 Jun 2013   Contributor(s):: Anisur Rahman
The improved transport properties of new channel materials, such as Ge and IIIV semiconductors, along with new device designs, such as dual gate, tri gate or FinFETs, are expected to enhance the performance of nanoscale CMOS devices. Novel process techniques, such as ALD, high# dielectrics,...

Nanoscale MOSFETS: Physics, Simulation and Design
27 Jun 2013   Contributor(s):: Zhibin Ren
This thesis discusses device physics, modeling and design issues of nanoscale transistors at the quantum level. The principle topics addressed in this report are 1) an implementation of appropriate physics and methodology in device modeling, 2)development of a new TCAD (technology computer aided...