See more compact models using the MIT Virtual Source (MVS) Model

The Stanford Virtual-Source Carbon Nanotube Field-Effect Transistors (VSCNFET) model is a semi-empirical compact model for CNFETs that captures the dimensional scaling properties and includes parasitic resistance, capacitance, and tunneling leakage currents. Inputs to the model are device design parameters such as gate length, gate oxide thickness, CNT diameter, and flat-band voltage. Experimental devices with the gate length down to 15 nm and numerical simulations based on the non-equilibrium Green’s function formalism are used for parameter extraction and model calibration. The model aims to assess the potentials of CNFET technology for the sub-10-nm technology nodes.

• Stanford Virtual-Source Carbon Nanotube Field-Effect Transistors Model 1.0.1 Verilog-A(VA | 25 KB)
• Stanford Virtual-Source Carbon Nanotube Field-Effect Transistors Model 1.0.1 Benchmarks(ZIP | 12 KB)
• Stanford Virtual-Source Carbon Nanotube Field-Effect Transistors Model 1.0.1 Parameters(TXT | 697 B )
• Stanford Virtual-Source Carbon Nanotube Field-Effect Transistors Model 1.0.1 Experimental Data(ZIP | 50 KB)
• Stanford Virtual-Source Carbon Nanotube Field-Effect Transistors Model 1.0.1 Manual(PDF | 2 MB)
• vscnfet_1_0_1_matlab_exerciser.zip(ZIP | 17 KB)
• vscnfet_1_0_1_qug.pdf(PDF | 663 KB)
• vscnfet_abs.txt(TXT | 573 B )
• License terms

C.-S. Lee, E. Pop, A. Franklin, W. Haensch, and H.-S. P. Wong, “A Compact Virtual-Source Model for Carbon Nanotube Field-Effect Transistors in the Sub-10-nm Regime—Part I: Intrinsic Elements,” arXiv:1503.04397

C.-S. Lee, E. Pop, A. Franklin, W. Haensch, and H.-S. P. Wong, “A Compact Virtual-Source Model for Carbon Nanotube Field-Effect Transistors in the Sub-10-nm Regime—Part II: Extrinsic Elements and Performance Assessment,” arXiv:1503.04398

Researchers should cite this work as follows:

• Chi-Shuen Lee; H.-S. Philip Wong (2015). Stanford Virtual-Source Carbon Nanotube Field-Effect Transistors Model. nanoHUB. doi:10.4231/D3BK16Q68

  BibTex | EndNote

Updates in version 1.0.1

1) Modified the charge model to avoid differentiation problem at Vds = 0

2) Removed unused and duplicate variables and hidden states in the Verilog-A file

3) Changed module name to vscnfet_1_0_1 to match with the Verilog-A file name vscnfet_1_0_1.va

4) Changed limexp() to exp() in all the non-genvar for-loops

5) Initialized the surface potential psys in the Verilog-A file