Device Options and Trade-offs for 5 nm CMOS Technology Seminar Series

By Mark Lundstrom

Electrical and Computer Engineering, Purdue University, West Lafayette, IN

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Abstract

Today's CMOS technology is so-called 14-nm technology.  10 nm technology development is well underway, and 7 nm has begun. It will soon be time to select a technology for the 5 nm node. To help understand the device options, what each on promises, what the challenges and trade-offs are, NEEDS has invited a group of leading experts to share their views with.  We are grateful for their willingness to participate and hope that these seminars spark in important discussion.

This seminar series complements a recent tutorial, “Emerging CMOS Technology at 5 nm and Beyond,” presented at the 2015 International Electron Devices Meeting. Selected presentation files from that tutorial are listed below:

Device Options and Tradeoffs
Mark Lundstrom and Xingshu Sun, Purdue University
Dimitri Antoniadis, MIT
Shalool Rakheja, New York University

BEOL Process Challenges
Takeshi Nogami, IBM Corporation

Emerging Interconnect Technologies
Krishna Saraswat, Stanford University

Advanced CMOS Device Physics for 7 nm and Beyond
Scott Thompson, University of Florida

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Researchers should cite this work as follows:

  • Mark Lundstrom (2015), "Device Options and Trade-offs for 5 nm CMOS Technology Seminar Series," https://nanohub.org/resources/22879.

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In This Series

  1. Nanometer-Scale III-V Electronics: from Quantum-Well Planar MOSFETs to Vertical Nanowire MOSFETs

    05 Oct 2015 | Online Presentations | Contributor(s): Juses A. del Alamo

    This talk will review recent progress as well as challenges confronting III-V electronics for future logic applications with emphasis on the presenter’s research activities at MIT.

  2. Inter-band Tunnel Transistors: Opportunities and Challenges

    30 Oct 2015 | Online Presentations | Contributor(s): Suman Datta

    In this talk, we will review progress in Tunnel FETs and also analyze primary roadblocks in the path towards achieving steep switching performance in III-V HTFET.

  3. Negative Capacitance Ferroelectric Transistors: A Promising Steep Slope Device Candidate?

    30 Oct 2015 | Online Presentations | Contributor(s): Suman Datta

    In this talk, we will review progress in non-perovskite ALD based ferroelectric dielectrics which have strong implication for VLSI compatible negative capacitance Ferroelectric FETs.

  4. Green Light on Germanium

    02 Nov 2015 | Online Presentations | Contributor(s): peide ye

    This talk will review recent progress as well as challenges on Ge research for future logic applications with emphasis on the breakthrough work at Purdue University on Ge nFET which leads to the demonstration of the world first Ge CMOS circuits on Si substrates. Ge device technology includes...

  5. A Tutorial Introduction to Negative-­Capacitor Landau Transistors: Perspectives on the Road Ahead

    04 Dec 2015 | Online Presentations | Contributor(s): Muhammad A. Alam

    In this talk, I use a simple graphical approach to demystify the device and explain why the experimental results are easy to misinterpret. Since the NC-FET is just a special case of a much broader class of phase-change devices and systems (e.g., transistors, memories, MEMS, logic-in-memory...