Future computing systems require research breakthroughs in:
- Robustness: Existing validation and test methods barely cope with today’s complexity. Reliability failures, largely benign in the past, are becoming visible at the system level.
- Performance: Energy benefits of silicon have plateaued (power wall). Abundant-data applications (e.g., machine learning) are increasingly dominated by off-chip memory accesses (memory wall).
- New applications: Neuro- and bio-sciences create tremendous opportunities for new computing systems: from implants to understanding brain functions.
This talk presents an overview of my group’s research in the above areas, and particularly emphasizes complexity and performance:
- QED and Symbolic QED dramatically improve pre-silicon verification and post-silicon validation. Difficult bugs can now be detected and localized automatically, in a few minutes to a few hours (vs. weeks or months of intense manual work today).
- N3XT leverages emerging nanotechnologies to create new architectures that overcome the memory wall and the power wall. N3XT targets 1,000X energy efficiency improvements for future computing systems. N3XT hardware prototypes are examples of transforming scientifically-interesting nanomaterials and nanodevices into actual nanosystems.
Subhasish Mitra is Professor of EE and of CS at Stanford University, where he directs the Stanford Robust Systems Group and co-leads the Computation focus area of the Stanford SystemX Alliance. He is also a faculty member of the Stanford Neurosciences Institute. Prof. Mitra holds the Carnot Chair of Excellence in Nanosystems at CEA-LETI in Grenoble, France. Before joining the Stanford faculty, he was a Principal Engineer at Intel Corporation. Prof. Mitra's research interests range broadly across robust computing, nanosystems, VLSI design, validation, test and electronic design automation, and neurosciences.
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PGSC 105, Purdue University, West Lafayette, IN