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Compact models are mathematical descriptions of semiconductor devices used in analog circuit simulation engines such as SPICE. A compact model provides a computationally efficient description of the terminal properties of a device as a function of terminal voltages:[{I}, {Q}] = f(Vg, Vd, Vs, Vb).

Compact Models on nanoHUB

Compact Models (1-20 of 48)

  1. WHiTe Compact Models

    19 Mar 2023 | Compact Models | Contributor(s):

    By Neal Graham Wood

    This package provides a set of 4H SiC (silicon carbide) high-temperature integrated device compact models, written in industry standard Verilog-A; currently included are a resistor and a JFET...

    https://nanohub.org/publications/339/?v=12

  2. Compact Model Vortex-STNO

    17 Nov 2022 | Compact Models | Contributor(s):

    By Sonal Shreya1, Farshad Moradi1

    Aarhus University, Denmark

    we present a Verilog-A-based analytical model of a vortex spin-torque nano oscillator (V-STNO) for enabling circuit-level simulation. The model presented here is functional for both linearand...

    https://nanohub.org/publications/532/?v=1

  3. WHiTe Compact Models

    14 Jun 2022 | Compact Models | Contributor(s):

    By Neal Graham Wood

    This package provides a set of 4H SiC (silicon carbide) high-temperature integrated device compact models, written in industry standard Verilog-A; currently included are a resistor and a JFET...

    https://nanohub.org/publications/339/?v=11

  4. THM-OTFT Compact Model

    24 May 2022 | Compact Models | Contributor(s):

    By Alexander Kloes1, Jakob Simon Leise1, Jakob Pruefer1, Aristeidis Nikolaou1, Ghader Darbandy1

    THM University of Applied Sciences

    Charge-based compact model for the DC and AC simulation of organic TFTs

    https://nanohub.org/publications/456/?v=1

  5. THM-TFET Compact Model

    30 Apr 2022 | Compact Models | Contributor(s):

    By Alexander Kloes1, Fabian Horst2, Anita Farokhnejad3, Michael Graef4

    1. Technische Hochschule Mittelhessen - University of Applied Sciences 2. Bender GmbH & Co. KG 3. IMEC 4. Infineon Technologies

    THM-TFET is a compact model for a double-gate Tunnel-FET, is provided in Verilog-A code and allows for DC, AC and transient circuit simulation.

    https://nanohub.org/publications/427/?v=1

  6. CCAM Compact Carbon Nanotube Field-Effect Transistor Model

    27 Apr 2022 | Compact Models | Contributor(s):

    By Michael Schroter1, Manojkumar Annamalai2, Max Haferlach3, Martin Claus3

    1. UCSD 2. Technische Universitaet Dresden 3. Technische Universität Dresden

    CCAM is a semi-physical carbon nanotube field-effect transistor model applicable for digital, analog and high frequency applications.

    https://nanohub.org/publications/62/?v=3

  7. PSPHV LDMOS

    19 Nov 2021 | Compact Models | Contributor(s):

    By Colin McAndrew1, kejun xia2

    1. NXP Semiconductors 2. TSMC

    This is an update to version 1.0.6 of the PSPHV LDMOS model (an enhanced PSP103.6 model for the core MOS transistor, an updated JFETIDG model for the drift region, JUNCAP2 for the pn-junction...

    https://nanohub.org/publications/475/?v=1

  8. WHiTe Compact Models

    30 Oct 2021 | Compact Models | Contributor(s):

    By Neal Graham Wood

    This package provides a set of 4H SiC (silicon carbide) high-temperature integrated device compact models, written in industry standard Verilog-A; currently included are a resistor and a JFET...

    https://nanohub.org/publications/339/?v=10

  9. Peking University Analog-Switching Resistive Random Access Memory (RRAM) Verilog-A model

    13 Jan 2021 | Compact Models | Contributor(s):

    By Lixia Han1, Linlin Cai1, Jinfeng Kang1, Xiaoyan Liu1, Peng Huang1

    Peking University

    The Peking University Analog-switching RRAM physical model can capture the pulse conductance updates of analog RRAM devices rapidly and accurately. The model is described by Verilog-A and can be...

    https://nanohub.org/publications/403/?v=1

  10. Florida Ferroelectric Tunnel Junction Device Model

    09 Sep 2020 | Compact Models | Contributor(s):

    By Tong Wu1, Jing Guo1

    University of Florida

    A compact model of the Ferroelectric Tunnel Junctions (FTJs) device is constructed, using the Wentzel–Kramers–Brillouin (WKB) approximation for tunneling current calculation.

    https://nanohub.org/publications/375/?v=1

  11. WHiTe (Wood-High-Temperature) Compact Models

    21 May 2020 | Compact Models | Contributor(s):

    By Neal Graham Wood

    This package provides a set of 4H silicon carbide high-temperature integrated device compact models, written in industry standard Verilog-A; currently included are a resistor and a junction...

    https://nanohub.org/publications/339/?v=4

  12. PSPHV LDMOS

    17 Apr 2020 | Compact Models | Contributor(s):

    By Colin McAndrew

    NXP Semiconductors

    PSPHV consists of an enhanced PSP103.6 model for thecore MOS transistor, an updated JFETIDG model for thedrift region, JUNCAP2 for the pn-junction diodes,and two 3-terminal MOS capacitors based on...

    https://nanohub.org/publications/347/?v=1

  13. WHiTe (Wood-High-Temperature) Compact Models

    16 Apr 2020 | Compact Models | Contributor(s):

    By Neal Wood

    Toshiba Europe Limited

    This package provides a set of 4H silicon carbide high-temperature integrated device compact models, written in industry standard Verilog-A; currently included are a resistor and a junction...

    https://nanohub.org/publications/339/?v=3

  14. WHiTe (Wood-High-Temperature) Compact Models

    10 Mar 2020 | Compact Models | Contributor(s):

    By Neal Graham Wood

    This package provides a set of 4H silicon carbide high-temperature integrated device compact models, written in industry standard Verilog-A; currently included are a resistor and a junction...

    https://nanohub.org/publications/339/?v=2

  15. WHiTe (Wood-High-Temperature) Compact Models

    25 Feb 2020 | Compact Models | Contributor(s):

    By Neal Graham Wood

    This package provides a set of 4H silicon carbide high-temperature integrated device compact models, written in industry standard Verilog-A; currently included are a resistor and a junction...

    https://nanohub.org/publications/339/?v=1

  16. EPFL HEMT MODEL

    14 Aug 2019 | Compact Models | Contributor(s):

    By Farzan Jazaeri1, jean-michel sallese, Majid Shalchian2, Matthias Bucher3, Nikolaos Makris4

    1. École Polytechnique Fédérale de Lausanne,(EPFL) 2. Amirkabir University of Tehnology 3. Technical University of Crete 4. ECE Technical University of Crete / IESL Foundation for Research and Technology-Hellas

    The EPFL HEMT Model is a design-oriented charge-based model for dc operation of AlGaAs/GaAs and AlGaN/GaN-based high-mobility field-effect transistors. The intrinsic model is physics-based and the...

    https://nanohub.org/publications/301/?v=1

  17. Unimore Resistive Random Access Memory (RRAM) Verilog-A Model

    22 May 2019 | Compact Models | Contributor(s):

    By Francesco Maria Puglisi1, Tommaso Zanotti1, Paolo Pavan1

    Università di Modena e Reggio Emilia

    The Unimore RRAM Verilog-A model is a physics-based compact model of bipolar RRAM which includes cycle-to-cycle variability, thermal effects, self-heating, and multilevel Random Telegraph Noise (RTN).

    https://nanohub.org/publications/289/?v=1

  18. Peking University Resistive-Switching Random Access Memory (RRAM) Verilog-A Model

    27 Mar 2019 | Compact Models | Contributor(s):

    By Weijie Xu1, Jinfeng Kang1

    Peking University

    The Peking University RRAM Model is a SPICE-compatible compact model which is designed for simulation of metal-oxide based RRAM devices. It captures typical DC and AC electrical behaviors of the...

    https://nanohub.org/publications/284/?v=1

  19. Stanford 2D Semiconductor (S2DS) Transistor Model

    11 Aug 2018 | Compact Models | Contributor(s):

    By Saurabh Vinayak Suryavanshi1, Eric Pop1

    Stanford University

    The Stanford 2D Semiconductor (S2DS) model is a physics-based, compact model for field-effect transistors (FETs) based on two-dimensional (2D) semiconductors such as MoS2.

    https://nanohub.org/publications/18/?v=3

  20. Multi-walled/Single-walled Carbon Nanotube (MWCNT/SWCNT) Interconnect Lumped Compact Model Considering Defects, Contact resistance and Doping impact

    11 Jul 2018 | Compact Models | Contributor(s):

    By Rongmei Chen1, Jie LIANG1, Jaehyun Lee2, Vihar Georgiev2, Aida Todri1

    1. CNRS 2. University of Glasgow

    In this project, we present SWCNT and MWCNT interconnect compact models. These models consider the impact of CNT defects, the chirality and contact resistance between CNT-electrode (Pd) on CNT...

    https://nanohub.org/publications/243/?v=1