Nanoelectronic Scaling Tradeoffs: What does Physics Have to Say?

By Victor Zhirnov

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"Investigation of adventurous new technological approaches is a high-risk enterprise… We …go too far and discourage critical assessments…It is the advocates who organize the conferences and the special issues of journals. The critic is likely to be left uncited. Those who are employed in the prevailing main line approach are, in any case likely just to shrug in skepticism. They will hesitate to invest the time needed for a detailed assessment of a possibility they consider unlikely"

Rolf Landauer

Beyond CMOS, several completely new approaches to information-processing and data-storage technologies and architectures are emerging to address the timeframe beyond the current SIA International Technology Roadmap for Semiconductors (ITRS). A wide range of new ideas have been proposed for post-CMOS technologies, such as spintronic, molecular electronics, quantum cellular automata, quantum computation etc. For the first time, the 2001 edition of the ITRS contained a chapter on "Emerging Research Devices". Characteristic of any new area, it is difficult to discern which of these concepts has the potential to provide a technological basis for information technologies of the future. However, since introduction of alternative nanoelectronics technologies is possible within a 15-year horizon, it is important to identify nanoelectronic technologies that have the potential to sustain our tradition of exponential improvements in cost-performance.

In this presentation, we examine the projections for the continued scaling of CMOS integrated circuit technology and look at some of the alternative directions that have been proposed for information processing technologies. The question we consider is: "What are the ultimate limits to the speed, size, density and dissipated energy of an arbitrary switch, allowed by the laws of physics?" A simple Gedanken experiment is described that seeks to comprehend the benefits of scaling in the nano-regime; e.g., to what extent are molecular, CNT, etc. technologies likely to be useful in continuing the benefits of scaling that we have enjoyed for over three decades? We use a simple potential barrier model for devices to argue that scaling for dense circuits is ultimately limited by power dissipation. This result is connected to fundamental physics of heat removal and leads to scaling limit estimates for maximally dense circuits. Our analysis suggests that perhaps these new nanotechnologies can offer only a limited extension to the scaling paradigm for electron transport devices. Finally we conclude the presentation by examining possible fruitful directions for research in information processing technologies.


Victor Zhirnov received the M.S. in applied physics from the Ural Polytechnic Institute, Ekaterinburg, Russia, and the Ph.D. in solid state electronics from the Institute of Physics and Technology, Moscow, in 1989 and 1992, respectively. From 1992 to 1998 he was a senior scientist at the Institute of Crystallography of Russian Academy of Science in Moscow.

Currently he is research associate professor at North Carolina State University. Victor Zhirnov also has an appointment as research scientists at the Semiconductor Research Corporation (SRC). His responsibilities at the SRC include assessments of emerging nanoelectronic devices.

Victor Zhirnov's research interests include properties of materials properties at nanoscale, deterministic doping of semiconductor nanostructures, tunneling phenomena, vacuum microelectronics and nanoelectronics. He has authored and co-authored over 80 technical papers and contributions to books. He has served as a consultant to a number of government, industrial, and academic institutions.

Springer Prize, and the Arthur K. Doolittle Award.

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Researchers should cite this work as follows:

  • Victor Zhirnov (2003), "Nanoelectronic Scaling Tradeoffs: What does Physics Have to Say?,"

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